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[PATCH] MIPS: Cleanup indentation and whitespace

To: ralf@linux-mips.org, linux-mips@linux-mips.org
Subject: [PATCH] MIPS: Cleanup indentation and whitespace
From: Tony Wu <tung7970@gmail.com>
Date: Fri, 21 Jun 2013 19:10:46 +0800
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Signed-off-by: Tony Wu <tung7970@gmail.com>
---
 arch/mips/include/asm/cpu-features.h               |   32 ++++++++++----------
 .../include/asm/mach-generic/kernel-entry-init.h   |    4 +--
 arch/mips/include/asm/processor.h                  |    4 +--
 arch/mips/kernel/branch.c                          |    1 -
 arch/mips/kernel/unaligned.c                       |    1 +
 arch/mips/mm/page.c                                |    2 +-
 6 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h 
b/arch/mips/include/asm/cpu-features.h
index df5e523..aee9bc1 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -87,13 +87,13 @@
 #define cpu_has_mips16         (cpu_data[0].ases & MIPS_ASE_MIPS16)
 #endif
 #ifndef cpu_has_mdmx
-#define cpu_has_mdmx          (cpu_data[0].ases & MIPS_ASE_MDMX)
+#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
 #endif
 #ifndef cpu_has_mips3d
-#define cpu_has_mips3d        (cpu_data[0].ases & MIPS_ASE_MIPS3D)
+#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
 #endif
 #ifndef cpu_has_smartmips
-#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
+#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
 #endif
 #ifndef cpu_has_rixi
 #define cpu_has_rixi           (cpu_data[0].options & MIPS_CPU_RIXI)
@@ -111,7 +111,7 @@
 #define cpu_has_ic_fills_f_dc  (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
 #endif
 #ifndef cpu_has_pindexed_dcache
-#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+#define cpu_has_pindexed_dcache        (cpu_data[0].dcache.flags & 
MIPS_CACHE_PINDEX)
 #endif
 #ifndef cpu_has_local_ebase
 #define cpu_has_local_ebase    1
@@ -151,18 +151,18 @@
 #ifndef cpu_has_mips_5
 # define cpu_has_mips_5                (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
 #endif
-# ifndef cpu_has_mips32r1
+#ifndef cpu_has_mips32r1
 # define cpu_has_mips32r1      (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
-# endif
-# ifndef cpu_has_mips32r2
+#endif
+#ifndef cpu_has_mips32r2
 # define cpu_has_mips32r2      (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
-# endif
-# ifndef cpu_has_mips64r1
+#endif
+#ifndef cpu_has_mips64r1
 # define cpu_has_mips64r1      (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
-# endif
-# ifndef cpu_has_mips64r2
+#endif
+#ifndef cpu_has_mips64r2
 # define cpu_has_mips64r2      (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
-# endif
+#endif
 
 /*
  * Shortcuts ...
@@ -184,9 +184,9 @@
  * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
  */
-# ifndef cpu_has_clo_clz
-# define cpu_has_clo_clz       cpu_has_mips_r
-# endif
+#ifndef cpu_has_clo_clz
+#define cpu_has_clo_clz        cpu_has_mips_r
+#endif
 
 #ifndef cpu_has_dsp
 #define cpu_has_dsp            (cpu_data[0].ases & MIPS_ASE_DSP)
@@ -212,7 +212,7 @@
 # define cpu_has_64bits                (cpu_data[0].isa_level & 
MIPS_CPU_ISA_64BIT)
 # endif
 # ifndef cpu_has_64bit_zero_reg
-# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# define cpu_has_64bit_zero_reg        (cpu_data[0].isa_level & 
MIPS_CPU_ISA_64BIT)
 # endif
 # ifndef cpu_has_64bit_gp_regs
 # define cpu_has_64bit_gp_regs         0
diff --git a/arch/mips/include/asm/mach-generic/kernel-entry-init.h 
b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
index 7e66505..13b0751 100644
--- a/arch/mips/include/asm/mach-generic/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
@@ -12,8 +12,8 @@
 /* Intentionally empty macro, used in head.S. Override in
  * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
  */
-.macro kernel_entry_setup
-.endm
+       .macro  kernel_entry_setup
+       .endm
 
 /*
  * Do SMP slave processor setup necessary before we can savely execute C code.
diff --git a/arch/mips/include/asm/processor.h 
b/arch/mips/include/asm/processor.h
index 1470b7b..b7d2aa3 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -231,8 +231,8 @@ struct thread_struct {
        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
        unsigned long error_code;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
-    struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
-    struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
+       struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
+       struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
 #endif
        struct mips_abi *abi;
 };
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 46c2ad0..4d78bf4 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -467,5 +467,4 @@ unaligned:
        printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
        force_sig(SIGBUS, current);
        return -EFAULT;
-
 }
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 3eaa02a..8eaf310 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -1549,6 +1549,7 @@ sigill:
            ("Unhandled kernel unaligned access or invalid instruction", regs);
        force_sig(SIGILL, current);
 }
+
 asmlinkage void do_ade(struct pt_regs *regs)
 {
        enum ctx_state prev_state;
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 4eb8dcf..2c0bd58 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -232,7 +232,7 @@ static inline void __cpuinit build_clear_pref(u32 **buf, 
int off)
 
                        uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
                }
-               }
+       }
 }
 
 extern u32 __clear_page_start;
-- 
1.7.10.2

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