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[PATCH V2] MIPS: flush TLB handlers before calling them

To: linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH V2] MIPS: flush TLB handlers before calling them
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 20 Jun 2013 22:29:42 +0200
Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>, Jayachandran C <jchandra@broadcom.com>, David Daney <david.daney@cavium.com>
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When having enabled MIPS_PGD_C0_CONTEXT, trap_init() might call the
generated tlbmiss_handler_setup_pgd before it was committed to memory,
causing boot failures:

  trap_init()
   |- per_cpu_trap_init()
   |   |- TLBMISS_HANDLER_SETUP()
   |       |- tlbmiss_handler_setup_pgd()
   |- flush_tlb_handlers()

To avoid this, move flush_tlb_handlers() into per_cpu_trap_init() to
ensure the generated handler is always committed on all cpus.

This issue was introduced in 3d8bfdd0307223de678962f1c1907a7cec549136
("MIPS: Use C0_KScratch (if present) to hold PGD pointer.").

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---

V1 -> V2:
 * Move flush_tlb_handlers into per_cpu_trap_init() to also fix it for
   !boot_cpu.

 arch/mips/kernel/traps.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 142d2be..b57f22b 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1807,6 +1807,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
                write_c0_wired(0);
        }
 #endif /* CONFIG_MIPS_MT_SMTC */
+       flush_tlb_handlers();
        TLBMISS_HANDLER_SETUP();
 }
 
@@ -1997,7 +1998,6 @@ void __init trap_init(void)
                set_handler(0x080, &except_vec3_generic, 0x80);
 
        local_flush_icache_range(ebase, ebase + 0x400);
-       flush_tlb_handlers();
 
        sort_extable(__start___dbe_table, __stop___dbe_table);
 
-- 
1.7.10.4


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