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[PATCH V2 2/2] MIPS: BCM63XX: Enable second core SMP on BCM6328 if avail

To: linux-mips@linux-mips.org
Subject: [PATCH V2 2/2] MIPS: BCM63XX: Enable second core SMP on BCM6328 if available
From: Jonas Gorski <jogo@openwrt.org>
Date: Tue, 18 Jun 2013 11:34:32 +0200
Cc: Ralf Baechle <ralf@linux-mips.org>, John Crispin <blogic@openwrt.org>, Maxime Bizon <mbizon@freebox.fr>, Florian Fainelli <florian@openwrt.org>, Kevin Cernekee <cernekee@gmail.com>
In-reply-to: <1371548072-6247-1-git-send-email-jogo@openwrt.org>
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BCM6328 has a OTP which tells us if the second core is available.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
 arch/mips/bcm63xx/prom.c                          |    6 +++++-
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    2 ++
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    7 +++++++
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index 33ddc78..f9ef7f7 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -67,7 +67,11 @@ void __init prom_init(void)
                 * for now.
                 */
                if (BCMCPU_IS_6328()) {
-                       bmips_smp_enabled = 0;
+                       reg = bcm_readl(BCM_6328_OTP_BASE +
+                                       OTP_USER_BITS_6328_REG(3));
+
+                       if (reg & OTP_6328_REG3_TP1_DISABLED)
+                               bmips_smp_enabled = 0;
                } else if (BCMCPU_IS_6358()) {
                        bmips_smp_enabled = 0;
                }
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h 
b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 3362289..6a3020d 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -235,6 +235,8 @@ enum bcm63xx_regs_set {
 #define BCM_6328_PCMDMAS_BASE          (0xdeadbeef)
 #define BCM_6328_RNG_BASE              (0xdeadbeef)
 #define BCM_6328_MISC_BASE             (0xb0001800)
+#define BCM_6328_OTP_BASE              (0xb0000600)
+
 /*
  * 6338 register sets base address
  */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h 
b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 3203fe4..ec97aa8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -1434,4 +1434,11 @@
 
 #define PCIE_DEVICE_OFFSET             0x8000
 
+/*************************************************************************
+ * _REG relative to RSET_OTP
+ *************************************************************************/
+
+#define OTP_USER_BITS_6328_REG(i)      (0x20 + (i) * 4)
+#define   OTP_6328_REG3_TP1_DISABLED   BIT(9)
+
 #endif /* BCM63XX_REGS_H_ */
-- 
1.7.10.4


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