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[PATCH V2 1/2] MIPS: BCM63XX: Add SMP support to prom.c

To: linux-mips@linux-mips.org
Subject: [PATCH V2 1/2] MIPS: BCM63XX: Add SMP support to prom.c
From: Jonas Gorski <jogo@openwrt.org>
Date: Tue, 18 Jun 2013 11:34:31 +0200
Cc: Ralf Baechle <ralf@linux-mips.org>, John Crispin <blogic@openwrt.org>, Maxime Bizon <mbizon@freebox.fr>, Florian Fainelli <florian@openwrt.org>, Kevin Cernekee <cernekee@gmail.com>
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From: Kevin Cernekee <cernekee@gmail.com>

This involves two changes to the BSP code:

1) register_smp_ops() for BMIPS SMP

2) The CPU1 boot vector on some of the BCM63xx platforms conflicts with
the special interrupt vector (IV).  Move it to 0x8000_0380 at boot time,
to resolve the conflict.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
[jogo@openwrt.org: moved SMP ops registration into ifdef guard,
 changed ifdef guards to if (IS_ENABLED())]
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
V1 -> V2:
 * changed ifdef guards to if (IS_ENABLED())

 arch/mips/bcm63xx/prom.c |   41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index fd69808..33ddc78 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -8,7 +8,11 @@
 
 #include <linux/init.h>
 #include <linux/bootmem.h>
+#include <linux/smp.h>
 #include <asm/bootinfo.h>
+#include <asm/bmips.h>
+#include <asm/smp-ops.h>
+#include <asm/mipsregs.h>
 #include <bcm63xx_board.h>
 #include <bcm63xx_cpu.h>
 #include <bcm63xx_io.h>
@@ -52,6 +56,43 @@ void __init prom_init(void)
 
        /* do low level board init */
        board_prom_init();
+
+       if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
+               /* set up SMP */
+               register_smp_ops(&bmips_smp_ops);
+
+               /*
+                * BCM6328 might not have its second CPU enabled, while BCM6358
+                * needs special handling for its shared TLB, so disable SMP
+                * for now.
+                */
+               if (BCMCPU_IS_6328()) {
+                       bmips_smp_enabled = 0;
+               } else if (BCMCPU_IS_6358()) {
+                       bmips_smp_enabled = 0;
+               }
+
+               if (!bmips_smp_enabled)
+                       return;
+
+               /*
+                * The bootloader has set up the CPU1 reset vector at
+                * 0xa000_0200.
+                * This conflicts with the special interrupt vector (IV).
+                * The bootloader has also set up CPU1 to respond to the wrong
+                * IPI interrupt.
+                * Here we will start up CPU1 in the background and ask it to
+                * reconfigure itself then go back to sleep.
+                */
+               memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
+               __sync();
+               set_c0_cause(C_SW0);
+               cpumask_set_cpu(1, &bmips_booted_mask);
+
+               /*
+                * FIXME: we really should have some sort of hazard barrier here
+                */
+       }
 }
 
 void __init prom_free_prom_memory(void)
-- 
1.7.10.4


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