I'm very glag to have chance to communicate with you in this maling list.
I'm involved in a SOC project making use of MIPS24K core.
While learning the CACHE aspects in Linux kernel source code v3.3.5, I
found the macro definition for cache operations.
It goes as:
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set push \n" \
" .set noreorder \n" \
" .set mips3\n\t \n" \
" cache %0, %1 \n" \
" .set pop \n" \
: "i" (op), "R" (*(unsigned char *)(addr)))
"i" (op) as argument 0 in CACHE instruction,
"R" (*(unsigned char *)(addr)) as argument 1 in CACHE instruction
Further, on the other hand, the CACHE instruction in MIPS ISA is like this:
Format: CACHE op, offset(base)
Purpose: Perform Cache Operation
To perform the cache operation specified by op.
And as know, depending on the op field, the offset(base) coud be
understood accordingly for different meanings.
Well, after the context, here below is what makes me confused.
In the cache_op inline assembly,
why "R" (*(unsigned char *)(addr)) is used as the argument 1 of CACHE
instruction, instead of "R" ((unsigned char *)(addr)) ?
the argument 1 numbered from 0 in CACHE instruction in MIPS ISA should be a
address with a offset, but from the code, it seems that the value in that
address is passed to CACHE instruction.
Could someone give some help on this?
I really appreciate that.
Thanks in advance.