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[PATCH V10 03/13] MIPS: Loongson: Introduce and use cpu_has_coherent_cac

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH V10 03/13] MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature
From: Huacai Chen <chenhc@lemote.com>
Date: Mon, 15 Apr 2013 20:46:58 +0800
Cc: John Crispin <john@phrozen.org>, linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>, Zhangjin Wu <wuzhangjin@gmail.com>, Huacai Chen <chenhc@lemote.com>, Hongliang Tao <taohl@lemote.com>, Hua Yan <yanh@lemote.com>
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Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
feature named cpu_has_coherent_cache and use it to modify MIPS's cache
flushing functions.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
---
 arch/mips/include/asm/cpu-features.h               |    3 +++
 .../asm/mach-loongson/cpu-feature-overrides.h      |    6 ++++++
 arch/mips/mm/c-r4k.c                               |   17 ++++++++++++++++-
 3 files changed, 25 insertions(+), 1 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h 
b/arch/mips/include/asm/cpu-features.h
index e5ec8fc..18b4db0 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -113,6 +113,9 @@
 #ifndef cpu_has_pindexed_dcache
 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
 #endif
+#ifndef cpu_has_coherent_cache
+#define cpu_has_coherent_cache 0
+#endif
 #ifndef cpu_has_local_ebase
 #define cpu_has_local_ebase    1
 #endif
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h 
b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index c0f3ef4..1b03d31 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -58,5 +58,11 @@
 #define cpu_has_vtag_icache    0
 #define cpu_has_watch          1
 #define cpu_has_local_ebase    0
+#ifdef CONFIG_CPU_SUPPORTS_COHERENT_CACHE
+#define cpu_has_coherent_cache 1
+#else
+#define cpu_has_coherent_cache 0
+#endif
+
 
 #endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index cab2aa2..edecf1c 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -341,7 +341,10 @@ static void __cpuinit r4k_blast_scache_setup(void)
 
 static inline void local_r4k___flush_cache_all(void * args)
 {
-#if defined(CONFIG_CPU_LOONGSON2)
+       if (cpu_has_coherent_cache && !cpu_has_dc_aliases)
+               return;
+
+#if defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_LOONGSON3)
        r4k_blast_scache();
        return;
 #endif
@@ -395,6 +398,9 @@ static inline void local_r4k_flush_cache_range(void * args)
        struct vm_area_struct *vma = args;
        int exec = vma->vm_flags & VM_EXEC;
 
+       if (cpu_has_coherent_cache && !cpu_has_dc_aliases)
+               return;
+
        if (!(has_valid_asid(vma->vm_mm)))
                return;
 
@@ -465,6 +471,9 @@ static inline void local_r4k_flush_cache_page(void *args)
        pte_t *ptep;
        void *vaddr;
 
+       if (cpu_has_coherent_cache && !cpu_has_dc_aliases)
+               return;
+
        /*
         * If ownes no valid ASID yet, cannot possibly have gotten
         * this page into the cache.
@@ -538,6 +547,9 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
 
 static inline void local_r4k_flush_data_cache_page(void * addr)
 {
+       if (cpu_has_coherent_cache && !cpu_has_dc_aliases)
+               return;
+
        r4k_blast_dcache_page((unsigned long) addr);
 }
 
@@ -670,6 +682,9 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
        unsigned long sc_lsize = cpu_scache_line_size();
        unsigned long addr = (unsigned long) arg;
 
+       if (cpu_has_coherent_cache && !cpu_has_dc_aliases)
+               return;
+
        R4600_HIT_CACHEOP_WAR_IMPL;
        if (dc_lsize)
                protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
-- 
1.7.7.3


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