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Re: [PATCH V2 02/16] MIPS: ralink: fix RT305x clock setup

To: John Crispin <blogic@openwrt.org>
Subject: Re: [PATCH V2 02/16] MIPS: ralink: fix RT305x clock setup
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Fri, 12 Apr 2013 17:00:01 +0400
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
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Hello.

On 12-04-2013 11:27, John Crispin wrote:

Add a few missing clocks.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
  arch/mips/ralink/rt305x.c |   13 ++++++++++++-
  1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index 0a4bbdc..64a0336 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
[...]
@@ -176,11 +177,21 @@ void __init ralink_clk_init(void)
                BUG();
        }

+       if (soc_is_rt3352() || soc_is_rt5350()) {
+               u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
+
+               if (!(val & RT3352_CLKCFG0_XTAL_SEL))
+                       wmac_rate = 20000000;
+       }
+
        ralink_clk_add("cpu", cpu_rate);
        ralink_clk_add("10000b00.spi", sys_rate);
        ralink_clk_add("10000100.timer", wdt_rate);
+       ralink_clk_add("10000120.watchdog", wdt_rate);
        ralink_clk_add("10000500.uart", uart_rate);
        ralink_clk_add("10000c00.uartlite", uart_rate);
+       ralink_clk_add("10100000.ethernet", sys_rate);
+       ralink_clk_add("wmac@10180000", wmac_rate);

   Are you sure it's not "10180000.wmac"?

WBR, Sergei


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