This set of patches enable the use of scratch registers on XLR/XLS and XLP
(cop0 reg 22, sel 0-7) to optimize the generated TLB handlers.
The current code assumes scratch is 31, which is fixed by the first patch.
The second patch enables use of a scratch register when it is available
even on a 32-bit or non-r2 platform. The third patch is a cleanup to
consolidate all the defines needed into one file, this patch does not
have any change in logic.
In the earlier scheme, if MIPS_PGD_C0_CONTEXT was defined, the Context
register or a scratch register would contain the current PGD, and the
Xcontext would contain the smp_processor_id shifted to index pointers.
In the new scheme, the behavior when MIPS_PGD_C0_CONTEXT is defined
remains the same. But when it is not defined, we still try to allocate
a scratch register for the current pgd. and the smp processor id remains
There is also an additional change is to generate the
tlbmiss_handler_setup_pgd() function even when MIPS_PGD_C0_CONTEXT is not
defined. This function will save the PGD in pgd_current and also in
the scratch register if one has been allocated.
Changes in v2:
* Update macros in thread-info.h, remove __ASSEMBLY__ part
* add ASM_CPUID_MFC0 and UASM_i_CPUID_MFC0 which allows us to remove
a lot of conditional compilation.
* make c0_kscratch a inline function and remove global variable
Jayachandran C (3):
MIPS: Allow platform specific scratch registers
MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT
MIPS: Move definition of SMP processor id register to header file
arch/mips/include/asm/mmu_context.h | 26 ++----
arch/mips/include/asm/stackframe.h | 26 ++----
arch/mips/include/asm/thread_info.h | 30 +++++-
arch/mips/kernel/cpu-probe.c | 1 +
arch/mips/mm/tlbex.c | 176 +++++++++++++++++------------------
5 files changed, 130 insertions(+), 129 deletions(-)