|Subject:||Re: [PATCH] MIPS: add irqdomain support for the CPU IRQ controller|
|From:||John Crispin <email@example.com>|
|Date:||Tue, 29 Jan 2013 19:32:43 +0100|
|List-software:||Ecartis version 1.0.0|
|References:||<firstname.lastname@example.org> <5106F7DC.email@example.com> <firstname.lastname@example.org>|
|User-agent:||Mozilla/5.0 (X11; Linux x86_64; rv:10.0.7) Gecko/20120922 Icedove/10.0.7|
Is it necessary to use the word 'intc'? What does that mean? Perhaps "mti,cpu-interrupt-controller"?
the name is only a detail and if you prefer said name i have no prolem with that.
Please use this as an actual device tree documentation binding.Yes, bindings should be documented in Documentation/devicetree/bindings/mips
Sure i will repost in a bit with a binding document
Just to satisfy my curiosity, Which drivers are using (or will be using) these mapping facilities? The timer and performance counters already work, so it isn't needed for them. What will use this.
we updated the ralink series i posted a few days ago to make use of this patch.
the SoC has its own irq controller behind STATUSF_IP2. STATUSF_IP5 is wired to ethernet and STATUSF_IP6 is wired to wifi i think on some socs from ralink the pci is wired to STATUSF_IP3to be able to nicely represent this in a devicetree we need an entry for the mips cpu interrupt controller.
as the patch no exists I am considering to update the lantiq code to make use of it. Also the patch originates from gabors ath79 devicetree series, which also makes use of it.
|<Prev in Thread]||Current Thread||[Next in Thread>|
|Previous by Date:||Re: [PATCH] MIPS: add irqdomain support for the CPU IRQ controller, David Daney|
|Next by Date:||[PATCH] MIPS: lantiq: fix cp0_perfcount_irq mapping, John Crispin|
|Previous by Thread:||Re: [PATCH] MIPS: add irqdomain support for the CPU IRQ controller, David Daney|
|Next by Thread:||[PATCH 1/2] NET: ethernet/netlogic: Netlogic XLR/XLS GMAC driver, ganesanr|
|Indexes:||[Date] [Thread] [Top] [All Lists]|