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Re: [PATCH 03/10] MIPS: PCI: Byteswap not needed in little-endian mode

To: Jayachandran C <jchandra@broadcom.com>
Subject: Re: [PATCH 03/10] MIPS: PCI: Byteswap not needed in little-endian mode
From: Sergei Shtylyov <sshtylyov@mvista.com>
Date: Tue, 15 Jan 2013 15:58:04 +0400
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
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Hello.

On 15-01-2013 10:19, Jayachandran C wrote:

Wrap the xlp_enable_pci_bswap() function and its call with
'#ifdef __BIG_ENDIAN'. On Netlogic XLP, the PCIe initialization code
to setup to byteswap is needed only in big-endian mode.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
---
  arch/mips/pci/pci-xlp.c |   12 +++++++++---
  1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
index 140557a..d201efa 100644
--- a/arch/mips/pci/pci-xlp.c
+++ b/arch/mips/pci/pci-xlp.c
@@ -191,8 +191,14 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
        return 0;
  }

-static int xlp_enable_pci_bswap(void)
+/*
+ * If big-endian, enable hardware byteswap on the PCIe bridges.
+ * This will make both the SoC and PCIe devices behave consistently with
+ * readl/writel.
+ */
+static void xlp_config_pci_bswap(void)
  {
+#ifdef __BIG_ENDIAN
        uint64_t pciebase, sysbase;
        int node, i;
        u32 reg;
@@ -222,7 +228,7 @@ static int xlp_enable_pci_bswap(void)
                reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
                nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
        }
-       return 0;
+#endif

You misunderstood. #ifdef within functions are frowned upon. Thios patch is hardly better than previous then.

WBR, Sergei


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