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RE: [PATCH v3] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.

To: David Daney <ddaney.cavm@gmail.com>
Subject: RE: [PATCH v3] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
From: "Hill, Steven" <sjhill@mips.com>
Date: Fri, 4 Jan 2013 18:24:54 +0000
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Cc: "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>, "ralf@linux-mips.org" <ralf@linux-mips.org>, "jchandra@broadcom.com" <jchandra@broadcom.com>
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Thread-topic: [PATCH v3] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
>> +#ifdef CONFIG_64BIT
>> +                     (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1));
>> +#else
>> +                     (PGDIR_SHIFT - PAGE_SHIFT - 1));
>> +#endif
>> +             UASM_i_INS(p, ptr, tmp, (PTE_T_LOG2 + 1),
>
> As far as I can tell, (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1) and
> (PGDIR_SHIFT - PAGE_SHIFT - 1) are the same thing.  So why the two cases?
>
>Can you give an example of where they might differ?
>
David,

Actually, no I cannot. The calculation was given to me by 'jchandra' and since 
I do not have 64-bit R2 hardware let alone the Broadcom platform, he said it 
worked on his platform and I took it from him as is. So does this patch work on 
Cavium platforms using both calculation methods? It would be nice if 'jchandra' 
could chime in, but he may be on holiday or something.

-Steve

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