Regarding commit a16dad7 [MIPS: Fix potencial corruption]

[Shmulik Ladkani <shmulik.ladkani@gmail.com>]

Hi,

Commit a16dad77 (MIPS: Fix potencial corruption) seems as a revert
of a8ca8b64 (MIPS: Avoid destructive invalidation on partial cachelines).

Snip of a16dad77:

@@ -643,9 +640,6 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned 
long size)
                         * hit ops with insufficient alignment.  Solved by
                         * aligning the address to cache line size.
                         */
-                       cache_op(Hit_Writeback_Inv_SD, addr & almask);
-                       cache_op(Hit_Writeback_Inv_SD,
-                                (addr + size - 1) & almask);


However,

(1)
The comment above the removed 'cache_op' instructions, which was
originally added as part of a8ca8b64, was not reverted, and now looks
out-of-context.

Any reason to keep the comment? If not, I'll submit a patch removing it.

(2)
Following a8ca8b64, another commit was submitted, adding similar
'cache_op' instructions to 'mips_sc_inv' - namely 96983ffe
(MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines).

Its purpose was to extend a8ca8b64, aligning behavior of 'mips_sc_inv'
to be similar to 'r4k_dma_cache_inv'.

Since the explicit 'cache_op' instrcutions are now removed from
'r4k_dma_cache_inv' (as of a16dad77), it probably makes sense to remove
them from 'mips_sc_inv' as well.

Any reason to keep these 'cache_op's? If not, I'll submit a patch.

Regards,
Shmulik