On Nov 26, 2012, at 1:53 PM, David Daney wrote:
> I have several general questions about this patch...
> On 11/21/2012 06:33 PM, Sanjay Lal wrote:
>> The following patchset implements KVM support for MIPS32R2 processors,
>> using Trap & Emulate, with basic runtime binary translation to improve
>> performance. The goal has been to keep the Guest kernel changes to a
> What is the point of minimizing guest kernel changes?
> Because you are using an invented memory map, instead of the architecturally
> defined map, there is no hope of running a single kernel image both natively
> and as a guest. So why do you care about how many changes there are.
It makes porting the code easier. Since we need a special guest kernel,
keeping the changes to minimum helps when migrating from one Linux version to
another. At this point we've migrated the code from 2.6.32 to 3.7 with 3.0
along the way, without any issues and anything more than an automatic merge.
>> The patch is against Linux 3.7-rc6. This is Version 2 of the patch set.
>> There is a companion patchset for QEMU that adds KVM support for the
>> MIPS target.
>> KVM/MIPS should support MIPS32-R2 processors and beyond.
>> It has been tested on the following platforms:
>> - Malta Board with FPGA based 34K (Little Endian).
>> - Sigma Designs TangoX board with a 24K based 8654 SoC (Little Endian).
>> - Malta Board with 74K @ 1GHz (Little Endian).
>> - OVPSim MIPS simulator from Imperas emulating a Malta board with
>> 24Kc and 1074Kc cores (Little Endian).
> Unlike x86, there is no concept of a canonical MIPS system for you to
> implement. So the choice of emulating a Malta or one of the SigmaDesigns
> boards doesn't seem to me to give you anything.
> Why not just define the guest system to be exactly the facilities provided by
> the VirtIO drivers?
The above list is a list of "host systems" that we've tested KVM/MIPS on. The
guest kernel runs on the Malta system that is emulated by QEMU regardless of
the host system.
And yes we do support VirtIO devices on the emulated Malta board to speed up
I/O, but since they attach to the emulated systems' PCI bus, we still need a
kernel and system that supports PCI.
Just an FYI, we'll be posting the QEMU patch set shortly.
> Perhaps it is obvious from the patches, but I wasn't able to figure out how
> you solve the problem of the Root/Host kernel clobbering the K0 and K1
> registers in its exception handlers. These registers are also used by the
> Guest kernel (aren't they)?
Yes k0/k1 do need to be saved as they are used by both the guest and host
kernels. The code is in kvm_locore.S around line 250 where the L1 exception
vectors are installed.