| To: | "Ralf Baechle" <ralf@linux-mips.org> |
|---|---|
| Subject: | Re: [PATCH 03/15] MIPS: Netlogic: select MIPSR2 for XLP |
| From: | "Jayachandran C." <jchandra@broadcom.com> |
| Date: | Wed, 7 Nov 2012 17:02:01 +0530 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <20121101102455.GA9437@jayachandranc.netlogicmicro.com> |
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| References: | <cover.1351688140.git.jchandra@broadcom.com> <3172102a3b041fdefbc721e3a25a95427bdec384.1351688140.git.jchandra@broadcom.com> <20121031132850.GB6365@linux-mips.org> <20121101102455.GA9437@jayachandranc.netlogicmicro.com> |
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On Thu, Nov 01, 2012 at 03:54:55PM +0530, Jayachandran C. wrote: > On Wed, Oct 31, 2012 at 02:28:50PM +0100, Ralf Baechle wrote: > > On Wed, Oct 31, 2012 at 06:31:29PM +0530, Jayachandran C wrote: > > > > > Disable PGD_C0_CONTEXT option for XLP, which does not work. > > > > Why does this not work on XLP? > > > > I see a kernel crash around the time init starts, planning to > look at this next. For now, I thought I will enable R2 and disable > PGD_C0_CONTEXT so that we get the rest of the R2 stuff for XLP. On XLP the XContext PTEbase is [63:55], but the current code tries to use XContext [63:48] to store the processor ID, which will not work. I can probably work around the issue by changing the shift from 51 to 58, but that would not leave enough space for the 128 cpu config we want to support. I will send patch to fix this and to use the XLP c0 scratch registers (cop0 $22) in the tlb handlers. But until the PGD_C0_CONTEXT code is updated, this patch is probably the best solution. JC. |
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