Re: [PATCH] MIPS: BCM63XX: add and use a clock for PCIe

[Florian Fainelli <florian@openwrt.org>]

On Sunday 28 October 2012 13:49:53 Jonas Gorski wrote:
> Add a PCIe clock and use that instead of directly touching the clock
> control register. While at it, fail if there is no such clock.

Looks good, thanks Jonas.

Acked-by: Florian Fainelli <florian@openwrt.org>

> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
> ---
>  arch/mips/bcm63xx/clk.c     |   15 +++++++++++++++
>  arch/mips/pci/pci-bcm63xx.c |   15 ++++++++++-----
>  2 files changed, 25 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
> index dff79ab..89a5fb0 100644
> --- a/arch/mips/bcm63xx/clk.c
> +++ b/arch/mips/bcm63xx/clk.c
> @@ -253,6 +253,19 @@ static struct clk clk_ipsec = {
>  };
>  
>  /*
> + * PCIe clock
> + */
> +
> +static void pcie_set(struct clk *clk, int enable)
> +{
> +     bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
> +}
> +
> +static struct clk clk_pcie = {
> +     .set    = pcie_set,
> +};
> +
> +/*
>   * Internal peripheral clock
>   */
>  static struct clk clk_periph = {
> @@ -313,6 +326,8 @@ struct clk *clk_get(struct device *dev, const char *id)
>               return &clk_pcm;
>       if (BCMCPU_IS_6368() && !strcmp(id, "ipsec"))
>               return &clk_ipsec;
> +     if (BCMCPU_IS_6328() && !strcmp(id, "pcie"))
> +             return &clk_pcie;
>       return ERR_PTR(-ENOENT);
>  }
>  
> diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
> index 8a48139..fa8c320 100644
> --- a/arch/mips/pci/pci-bcm63xx.c
> +++ b/arch/mips/pci/pci-bcm63xx.c
> @@ -11,6 +11,7 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/delay.h>
> +#include <linux/clk.h>
>  #include <asm/bootinfo.h>
>  
>  #include "pci-bcm63xx.h"
> @@ -119,11 +120,6 @@ static void __init bcm63xx_reset_pcie(void)
>  {
>       u32 val;
>  
> -     /* enable clock */
> -     val = bcm_perf_readl(PERF_CKCTL_REG);
> -     val |= CKCTL_6328_PCIE_EN;
> -     bcm_perf_writel(val, PERF_CKCTL_REG);
> -
>       /* enable SERDES */
>       val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
>       val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
> @@ -150,10 +146,19 @@ static void __init bcm63xx_reset_pcie(void)
>       mdelay(200);
>  }
>  
> +static struct clk *pcie_clk;
> +
>  static int __init bcm63xx_register_pcie(void)
>  {
>       u32 val;
>  
> +     /* enable clock */
> +     pcie_clk = clk_get(NULL, "pcie");
> +     if (IS_ERR_OR_NULL(pcie_clk))
> +             return -ENODEV;
> +
> +     clk_prepare_enable(pcie_clk);
> +
>       bcm63xx_reset_pcie();
>  
>       /* configure the PCIe bridge */
> -- 
> 1.7.2.5
>