[PATCH] MIPS:CMP Fix physical core number calculation logic

[jerin jacob <jerinjacobk@gmail.com>]

CPUNum Field in EBase register is 10bit wide, so after 1 bit right shift, mask
value should be 0x1ff

Signed-off-by: jerin jacob <jerinjacobk@gmail.com>
---
 arch/mips/kernel/smp-cmp.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index afc379c..06cd0c6 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -97,7 +97,7 @@ static void cmp_init_secondary(void)
 
        /* Enable per-cpu interrupts: platform specific */
 
-       c->core = (read_c0_ebase() >> 1) & 0xff;
+       c->core = (read_c0_ebase() >> 1) & 0x1ff;
 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
        c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
 #endif
-- 
1.7.6.5