linux-mips
[Top] [All Lists]

Re: [PATCH 0/2] Add RI and XI bits to MIPS base architecture.

To: "Steven J. Hill" <sjhill@mips.com>, ralf@linux-mips.org
Subject: Re: [PATCH 0/2] Add RI and XI bits to MIPS base architecture.
From: David Daney <ddaney.cavm@gmail.com>
Date: Wed, 12 Sep 2012 10:47:24 -0700
Cc: linux-mips@linux-mips.org
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=qkCcQGO3p2TVTvWfJKYhqNdRHh8A4tx7QyEIYSBv6wI=; b=d+puFmdSpQ8qCxMGg3AG+WlUPwCzhJPnBKzQ7MjXDpjkxT7EBuk6LHcp+o+1M3fQEZ 9w1i4X30JMhPzV93EhQ7jclJd1wzZdzYj66U7IgvLTNLqgKuzFofsJ0h0aCN/lGtn8FQ JUSMWcc+9/TT9HnWZbDNEw5hhO+2DdWK7LxA4z/ZXYhe81kSDPfXjtZ7hq5yveQ3utjL d5X721R1lsfeX03lnxZTo/9NZtwJJZN1mH+8IZ6qzaCNtHOaSKU6nEorwyBVYPDYlshs ScQkDPUDMtdtuFcFQefOX+HjMUOn71TfSvy5ZwNaVA4R1tIKn9NlOSXABFoGp+0TkzHX GTWw==
In-reply-to: <1347469309-11468-1-git-send-email-sjhill@mips.com>
List-archive: <http://www.linux-mips.org/archives/linux-mips/>
List-help: <mailto:ecartis@linux-mips.org?Subject=help>
List-id: linux-mips <linux-mips.eddie.linux-mips.org>
List-owner: <mailto:ralf@linux-mips.org>
List-post: <mailto:linux-mips@linux-mips.org>
List-software: Ecartis version 1.0.0
List-subscribe: <mailto:ecartis@linux-mips.org?subject=subscribe%20linux-mips>
List-unsubscribe: <mailto:ecartis@linux-mips.org?subject=unsubscribe%20linux-mips>
References: <1347469309-11468-1-git-send-email-sjhill@mips.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:15.0) Gecko/20120828 Thunderbird/15.0
On 09/12/2012 10:01 AM, Steven J. Hill wrote:
From: "Steven J. Hill" <sjhill@mips.com>

Add MIPSr3(TM) base architecture TLB support for Read Inhibit (RI)
and Execute Inhibit (XI) page protection. SmartMIPS cores will not
notice any change in functionality.

This patchset obsoletes the previous patchset with four commits.

Signed-off-by: Steven J. Hill <sjhill@mips.com>

FWIW:  I haven't tested it, but the entire set ...

Acked-by: David Daney <david.daney@cavium.com>



Steven J. Hill (2):
   MIPS: Add base architecture support for RI and XI.
   MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.

  arch/mips/include/asm/cpu-features.h               |    4 ++--
  arch/mips/include/asm/cpu.h                        |    1 +
  .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    2 +-
  arch/mips/include/asm/mipsregs.h                   |    1 +
  arch/mips/include/asm/pgtable-bits.h               |   18 +++++++++---------
  arch/mips/include/asm/pgtable.h                    |   12 ++++++------
  arch/mips/kernel/cpu-probe.c                       |    6 +++++-
  arch/mips/mm/cache.c                               |    2 +-
  arch/mips/mm/fault.c                               |    2 +-
  arch/mips/mm/tlb-r4k.c                             |    2 +-
  arch/mips/mm/tlbex.c                               |   14 +++++++-------
  11 files changed, 35 insertions(+), 29 deletions(-)



<Prev in Thread] Current Thread [Next in Thread>