[PATCH 0/2] Add RI and XI bits to MIPS base architecture.

["Steven J. Hill" <sjhill@mips.com>]

From: "Steven J. Hill" <sjhill@mips.com>

Add MIPSr3(TM) base architecture TLB support for Read Inhibit (RI)
and Execute Inhibit (XI) page protection. SmartMIPS cores will not
notice any change in functionality.

This patchset obsoletes the previous patchset with four commits.

Signed-off-by: Steven J. Hill <sjhill@mips.com>

Steven J. Hill (2):
  MIPS: Add base architecture support for RI and XI.
  MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.

 arch/mips/include/asm/cpu-features.h               |    4 ++--
 arch/mips/include/asm/cpu.h                        |    1 +
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    2 +-
 arch/mips/include/asm/mipsregs.h                   |    1 +
 arch/mips/include/asm/pgtable-bits.h               |   18 +++++++++---------
 arch/mips/include/asm/pgtable.h                    |   12 ++++++------
 arch/mips/kernel/cpu-probe.c                       |    6 +++++-
 arch/mips/mm/cache.c                               |    2 +-
 arch/mips/mm/fault.c                               |    2 +-
 arch/mips/mm/tlb-r4k.c                             |    2 +-
 arch/mips/mm/tlbex.c                               |   14 +++++++-------
 11 files changed, 35 insertions(+), 29 deletions(-)

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1.7.9.5