[PATCH 0/4] Add RI and XI bits to MIPS base architecture.

["Steven J. Hill" <sjhill@mips.com>]

From: "Steven J. Hill" <sjhill@mips.com>

Add MIPSr3(TM) base architecture TLB support for Read Inhibit (RI)
and Execute Inhibit (XI) page protection. SmartMIPS cores will not
notice any change in functionality.

Signed-off-by: Steven J. Hill <sjhill@mips.com>

Steven J. Hill (4):
  MIPS: Add base architecture support for RI and XI.
  MIPS: Remove kernel_uses_smartmips_rixi use from arch/mips/mm.
  MIPS: Remove kernel_uses_smartmips_rixi from page table bits.
  MIPS: Remove kernel_uses_smartmips_rixi macro definition.

 arch/mips/include/asm/cpu-features.h               |    7 ++++--
 arch/mips/include/asm/cpu.h                        |    2 ++
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    2 --
 arch/mips/include/asm/mipsregs.h                   |    1 +
 arch/mips/include/asm/pgtable-bits.h               |   24 ++++++++++++--------
 arch/mips/include/asm/pgtable.h                    |   12 +++++-----
 arch/mips/kernel/cpu-probe.c                       |   12 +++++++++-
 arch/mips/mm/cache.c                               |    2 +-
 arch/mips/mm/fault.c                               |    4 +++-
 arch/mips/mm/tlb-r4k.c                             |    7 ++++--
 arch/mips/mm/tlbex.c                               |   14 ++++++------
 11 files changed, 55 insertions(+), 32 deletions(-)

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1.7.9.5