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Re: [PATCH v2 3/3] MIPS: BCM47xx: rewrite GPIO handling and use gpiolib

To: Rafał Miłecki <zajec5@gmail.com>
Subject: Re: [PATCH v2 3/3] MIPS: BCM47xx: rewrite GPIO handling and use gpiolib
From: "Arend van Spriel" <arend@broadcom.com>
Date: Thu, 16 Aug 2012 20:43:11 +0200
Cc: "Florian Fainelli" <florian@openwrt.org>, "Hauke Mehrtens" <hauke@hauke-m.de>, ralf@linux-mips.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, john@phrozen.org
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On 08/16/2012 07:39 PM, Rafał Miłecki wrote:
2012/8/16 Florian Fainelli<florian@openwrt.org>:
>>+void __init bcm47xx_gpio_init(void)
>>+{
>>+     int err;
>>+
>>+     switch (bcm47xx_bus_type) {
>>+#ifdef CONFIG_BCM47XX_SSB
>>+     case BCM47XX_BUS_TYPE_SSB:
>>+             bcm47xx_gpio_count = ssb_gpio_count(&bcm47xx_bus.ssb);
>>+#endif
>>+#ifdef CONFIG_BCM47XX_BCMA
>>+     case BCM47XX_BUS_TYPE_BCMA:
>>+             bcm47xx_gpio_count = bcma_gpio_count(&bcm47xx_bus.bcma.bus);
>>+#endif
>>+     }
>
>Is this exclusive? Cannot we have both SSB and BCMA on the same device?
This applies to SoC only, so I believe it's fine. We don't have SoCs
based on BCMA and SSB at the same time.

It is indeed more than unlikely for a chip to have two silicon interconnects, which is what SSB and BCMA are. However, it does look suspicious from a code reading perspective. So I general I stick to the rule that each case must have a break and fall-thru are clearly commented.

You can find devices with multiple buses, but additional ones are
connected via PCIE or USB interface (or some other I don't know
about).

-- Rafał

Gr. AvS


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