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[PATCH 4/4] MIPS: lantiq: enable pci clk conditional for xrx200 SoC

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH 4/4] MIPS: lantiq: enable pci clk conditional for xrx200 SoC
From: John Crispin <blogic@openwrt.org>
Date: Thu, 16 Aug 2012 11:25:42 +0200
Cc: linux-mips@linux-mips.org, John Crispin <blogic@openwrt.org>
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The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/xway/sysctrl.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 8863cca..655c210 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -149,7 +149,8 @@ static int pci_enable(struct clk *clk)
 {
        unsigned int val = ltq_cgu_r32(ifccr);
        /* set bus clock speed */
-       if (of_machine_is_compatible("lantiq,ar9")) {
+       if (of_machine_is_compatible("lantiq,ar9") ||
+                       of_machine_is_compatible("lantiq,vr9")) {
                val &= ~0x1f00000;
                if (clk->rate == CLOCK_33M)
                        val |= 0xe00000;
-- 
1.7.9.1


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