[PATCH 02/12] MIPS: Netlogic: Fix low-level flush on core wakeup

["Jayachandran C" <jayachandranc@netlogicmicro.com>]

The L1D cache flush needs to be done for more iterations to ensure
that the cache is clean before waking up threads.

This change is experimental, but should not have any negative impact.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
---
 arch/mips/netlogic/common/smpboot.S |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/netlogic/common/smpboot.S 
b/arch/mips/netlogic/common/smpboot.S
index 7badf38..8c13cd9 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -84,7 +84,7 @@
        li      t0, LSU_DEBUG_DATA0
        li      t1, LSU_DEBUG_ADDR
        li      t2, 0           /* index */
-       li      t3, 0x200       /* loop count, 512 sets */
+       li      t3, 0x1000      /* loop count */
 1:
        sll     v0, t2, 5
        mtcr    zero, t0
-- 
1.7.9.5