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Re: [PATCH V3 11/16] drm/radeon: Make radeon card usable for Loongson.

To: Arnaud Patard <arnaud.patard@rtp-net.org>
Subject: Re: [PATCH V3 11/16] drm/radeon: Make radeon card usable for Loongson.
From: Ralf Baechle <ralf@linux-mips.org>
Date: Fri, 22 Jun 2012 12:06:19 +0100
Cc: Huacai Chen <chenhuacai@gmail.com>, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Fuxin Zhang <zhangfx@lemote.com>, Zhangjin Wu <wuzhangjin@gmail.com>, Huacai Chen <chenhc@lemote.com>, Hongliang Tao <taohl@lemote.com>, Hua Yan <yanh@lemote.com>, dri-devel@lists.freedesktop.org
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On Fri, Jun 22, 2012 at 11:39:19AM +0200, Arnaud Patard wrote:

> > --- a/drivers/gpu/drm/drm_vm.c
> > +++ b/drivers/gpu/drm/drm_vm.c
> > @@ -62,7 +62,7 @@ static pgprot_t drm_io_prot(uint32_t map_type, struct 
> > vm_area_struct *vma)
> >             tmp = pgprot_writecombine(tmp);
> >     else
> >             tmp = pgprot_noncached(tmp);
> > -#elif defined(__sparc__) || defined(__arm__)
> > +#elif defined(__sparc__) || defined(__arm__) || defined(__mips__)
> >     tmp = pgprot_noncached(tmp);
> 
> btw, would it be a good idea to use uncached accelerated instead ?

Not unconditionally.  Only some MIPS cores support uncached accelerated.
Basically you can only assume that cache modes 2 (uncached) (3 cachable
non-coherent) are supported.  On a SMP system use of 2 and 3 may be
unwise (SGI IP27 and IP35 may throw obscure exceptions to indicate their
dislike of these.) and on multi-processor systems there is mode 5, which
is cachable coherent.

The necessary logic is too complex to got into drm_io_prot() which already
is an #ifdef mess anyway so that function should be changed to call some
sort of architecutre specific hook so that function should be changed to
call some sort of architecture specific hook...

  Ralf

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