Re: [PATCH 2/2] gpio/MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins.

[David Daney <david.daney@cavium.com>]

On 05/17/2012 01:50 PM, Grant Likely wrote:
> On Thu, 12 Apr 2012 17:10:20 -0700, David Daney<ddaney.cavm@gmail.com>  wrote:
> > From: David Daney<david.daney@cavium.com>
> >
> > The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip
> > GPIO pins, this driver handles them all.  Configuring the pins as
> > interrupt sources is handled elsewhere (OCTEON's irq handling code).
> >
> > Signed-off-by: David Daney<david.daney@cavium.com>
> Aside from the bugs already pointed out;
>
> Acked-by: Grant Likely<grant.likely@secretlab.ca>
>
> Will you merge this series via the MIPS tree, or do I need to pick it
> up?
Thanks Grant.

I will make the fixes and resubmit.  I expect Ralf can merge these along 
with the rest of the pile of OCTEON patches.
David Daney

> > ---
> >   drivers/gpio/Kconfig       |    8 ++
> >   drivers/gpio/Makefile      |    1 +
> >   drivers/gpio/gpio-octeon.c |  166 ++++++++++++++++++++++++++++++++++++++++++++