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Re: [PATCH 2/2] spi: Add SPI master controller for OCTEON SOCs.

To: David Daney <ddaney.cavm@gmail.com>
Subject: Re: [PATCH 2/2] spi: Add SPI master controller for OCTEON SOCs.
From: Linus Walleij <linus.walleij@linaro.org>
Date: Mon, 14 May 2012 22:07:05 +0200
Cc: devicetree-discuss@lists.ozlabs.org, Grant Likely <grant.likely@secretlab.ca>, Rob Herring <rob.herring@calxeda.com>, spi-devel-general@lists.sourceforge.net, linux-mips@linux-mips.org, David Daney <david.daney@cavium.com>, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org
In-reply-to: <1336772086-17248-3-git-send-email-ddaney.cavm@gmail.com>
References: <1336772086-17248-1-git-send-email-ddaney.cavm@gmail.com> <1336772086-17248-3-git-send-email-ddaney.cavm@gmail.com>
Sender: linux-mips-bounce@linux-mips.org
On Fri, May 11, 2012 at 11:34 PM, David Daney <ddaney.cavm@gmail.com> wrote:

> +       mpi_cfg.u64 = 0;
> +       mpi_cfg.u64 |= p->cs_enax;
> +       if (mpi_cfg.u64 != p->last_cfg) {

But now I see why this 64bit is so clever. Forget the comment on 1/2!
This has a certain elegance to it that I just learned to appreciate.

Yours,
Linus Walleij

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