| To: | Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> |
|---|---|
| Subject: | RE: [PATCH 01/10] MIPS: Add core files for MIPS SEAD-3 development platform. |
| From: | "Hill, Steven" <sjhill@mips.com> |
| Date: | Mon, 7 May 2012 20:16:31 +0000 |
| Accept-language: | en-US |
| Cc: | "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>, "ralf@linux-mips.org" <ralf@linux-mips.org>, "Leung, Douglas" <douglas@mips.com>, "Dearman, Chris" <chris@mips.com> |
| In-reply-to: | <4F8386C8.9020401@renesas.com> |
| References: | <1333817315-30091-1-git-send-email-sjhill@mips.com> <1333817315-30091-2-git-send-email-sjhill@mips.com>,<4F8386C8.9020401@renesas.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| Thread-index: | AQHNFN5TXaIyKURn50SCHT0BxYKwcJaTtvkAgCs4fmA= |
| Thread-topic: | [PATCH 01/10] MIPS: Add core files for MIPS SEAD-3 development platform. |
Kuribayashi-san, I will certainly remove CONFIG_CPU_HAS_LLSC, thank you. I attempted to enable 'cpu_has_clo_clz' for SEAD-3, but it breaks my microMIPS-only kernel builds. Specifically, since microMIPS LL/SC instructions do not have 16-bit address offsets, in the '__cmpxchg_asm' macro function I get constraint errors because then the assembler has to use the %LO register in order to calculate the offset address. I am going to hold off on enabling the option until after the 3.5 release and then revisit for a solution. Thank you. -Steve |
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