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[PATCH 2/8] MIPS: OCTEON: Update register definitions.

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH 2/8] MIPS: OCTEON: Update register definitions.
From: David Daney <ddaney.cavm@gmail.com>
Date: Fri, 27 Apr 2012 11:32:34 -0700
Cc: David Daney <david.daney@cavium.com>
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From: David Daney <david.daney@cavium.com>

Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX.

Add little-endian register layouts.

Patch cvmx-interrupt-rsl.c for changed definition.

Signed-off-by: David Daney <david.daney@cavium.com>
---
 .../cavium-octeon/executive/cvmx-interrupt-rsl.c   |    2 +-
 arch/mips/include/asm/octeon/cvmx-agl-defs.h       | 1014 ++-
 arch/mips/include/asm/octeon/cvmx-asxx-defs.h      |  300 +-
 arch/mips/include/asm/octeon/cvmx-ciu-defs.h       |11333 ++++++++++++++++----
 arch/mips/include/asm/octeon/cvmx-ciu2-defs.h      | 7108 ++++++++++++
 arch/mips/include/asm/octeon/cvmx-dbg-defs.h       |   39 +-
 arch/mips/include/asm/octeon/cvmx-dpi-defs.h       |  411 +-
 arch/mips/include/asm/octeon/cvmx-fpa-defs.h       | 1321 +++-
 arch/mips/include/asm/octeon/cvmx-gmxx-defs.h      | 4966 ++++++++-
 arch/mips/include/asm/octeon/cvmx-gpio-defs.h      |  282 +-
 arch/mips/include/asm/octeon/cvmx-iob-defs.h       |  722 ++-
 arch/mips/include/asm/octeon/cvmx-ipd-defs.h       | 1111 ++-
 arch/mips/include/asm/octeon/cvmx-l2c-defs.h       | 1726 +++-
 arch/mips/include/asm/octeon/cvmx-l2d-defs.h       |  171 +-
 arch/mips/include/asm/octeon/cvmx-l2t-defs.h       |  105 +-
 arch/mips/include/asm/octeon/cvmx-led-defs.h       |   67 +-
 arch/mips/include/asm/octeon/cvmx-mio-defs.h       | 1909 ++++-
 arch/mips/include/asm/octeon/cvmx-mixx-defs.h      |  234 +-
 arch/mips/include/asm/octeon/cvmx-npei-defs.h      | 1743 +++-
 arch/mips/include/asm/octeon/cvmx-npi-defs.h       | 1260 +++-
 arch/mips/include/asm/octeon/cvmx-pci-defs.h       |  909 ++-
 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h   | 1292 +++-
 arch/mips/include/asm/octeon/cvmx-pcsx-defs.h      |  729 ++-
 arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h     |  574 +-
 arch/mips/include/asm/octeon/cvmx-pemx-defs.h      |  288 +-
 arch/mips/include/asm/octeon/cvmx-pescx-defs.h     |  246 +-
 arch/mips/include/asm/octeon/cvmx-pexp-defs.h      |    2 +-
 arch/mips/include/asm/octeon/cvmx-pip-defs.h       | 2431 ++++-
 arch/mips/include/asm/octeon/cvmx-pko-defs.h       | 1993 ++++-
 arch/mips/include/asm/octeon/cvmx-pow-defs.h       |  530 +-
 arch/mips/include/asm/octeon/cvmx-rnm-defs.h       |  107 +-
 arch/mips/include/asm/octeon/cvmx-sli-defs.h       | 1351 +++-
 arch/mips/include/asm/octeon/cvmx-smix-defs.h      |  202 +-
 arch/mips/include/asm/octeon/cvmx-spxx-defs.h      |  225 +-
 arch/mips/include/asm/octeon/cvmx-sriox-defs.h     |  703 ++-
 arch/mips/include/asm/octeon/cvmx-srxx-defs.h      |   62 +-
 arch/mips/include/asm/octeon/cvmx-stxx-defs.h      |  166 +-
 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h     |  268 +-
 38 files changed, 44862 insertions(+), 3040 deletions(-)
 create mode 100644 arch/mips/include/asm/octeon/cvmx-ciu2-defs.h

diff --git a/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c 
b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
index bea7538..560e034 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
@@ -130,7 +130,7 @@ void __cvmx_interrupt_gmxx_enable(int interface)
        if (num_ports) {
                if (OCTEON_IS_MODEL(OCTEON_CN38XX)
                    || OCTEON_IS_MODEL(OCTEON_CN58XX))
-                       gmx_tx_int_en.s.ncb_nxa = 1;
+                       gmx_tx_int_en.cn38xx.ncb_nxa = 1;
                gmx_tx_int_en.s.pko_nxa = 1;
        }
        gmx_tx_int_en.s.undflw = (1 << num_ports) - 1;
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h 
b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
index 30d68f2..542ee09 100644
--- a/arch/mips/include/asm/octeon/cvmx-agl-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -106,6 +106,7 @@
 union cvmx_agl_gmx_bad_reg {
        uint64_t u64;
        struct cvmx_agl_gmx_bad_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_38_63:26;
                uint64_t txpsh1:1;
                uint64_t txpop1:1;
@@ -120,8 +121,25 @@ union cvmx_agl_gmx_bad_reg {
                uint64_t reserved_4_21:18;
                uint64_t out_ovr:2;
                uint64_t reserved_0_1:2;
+#else
+               uint64_t reserved_0_1:2;
+               uint64_t out_ovr:2;
+               uint64_t reserved_4_21:18;
+               uint64_t loststat:2;
+               uint64_t reserved_24_25:2;
+               uint64_t statovr:1;
+               uint64_t reserved_27_31:5;
+               uint64_t ovrflw:1;
+               uint64_t txpop:1;
+               uint64_t txpsh:1;
+               uint64_t ovrflw1:1;
+               uint64_t txpop1:1;
+               uint64_t txpsh1:1;
+               uint64_t reserved_38_63:26;
+#endif
        } s;
        struct cvmx_agl_gmx_bad_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_38_63:26;
                uint64_t txpsh1:1;
                uint64_t txpop1:1;
@@ -136,9 +154,26 @@ union cvmx_agl_gmx_bad_reg {
                uint64_t reserved_4_21:18;
                uint64_t out_ovr:2;
                uint64_t reserved_0_1:2;
+#else
+               uint64_t reserved_0_1:2;
+               uint64_t out_ovr:2;
+               uint64_t reserved_4_21:18;
+               uint64_t loststat:1;
+               uint64_t reserved_23_25:3;
+               uint64_t statovr:1;
+               uint64_t reserved_27_31:5;
+               uint64_t ovrflw:1;
+               uint64_t txpop:1;
+               uint64_t txpsh:1;
+               uint64_t ovrflw1:1;
+               uint64_t txpop1:1;
+               uint64_t txpsh1:1;
+               uint64_t reserved_38_63:26;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_bad_reg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_35_63:29;
                uint64_t txpsh:1;
                uint64_t txpop:1;
@@ -150,32 +185,64 @@ union cvmx_agl_gmx_bad_reg {
                uint64_t reserved_3_21:19;
                uint64_t out_ovr:1;
                uint64_t reserved_0_1:2;
+#else
+               uint64_t reserved_0_1:2;
+               uint64_t out_ovr:1;
+               uint64_t reserved_3_21:19;
+               uint64_t loststat:1;
+               uint64_t reserved_23_25:3;
+               uint64_t statovr:1;
+               uint64_t reserved_27_31:5;
+               uint64_t ovrflw:1;
+               uint64_t txpop:1;
+               uint64_t txpsh:1;
+               uint64_t reserved_35_63:29;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
+       struct cvmx_agl_gmx_bad_reg_s cn61xx;
        struct cvmx_agl_gmx_bad_reg_s cn63xx;
        struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
+       struct cvmx_agl_gmx_bad_reg_s cn66xx;
+       struct cvmx_agl_gmx_bad_reg_s cn68xx;
+       struct cvmx_agl_gmx_bad_reg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_bist {
        uint64_t u64;
        struct cvmx_agl_gmx_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_25_63:39;
                uint64_t status:25;
+#else
+               uint64_t status:25;
+               uint64_t reserved_25_63:39;
+#endif
        } s;
        struct cvmx_agl_gmx_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t status:10;
+#else
+               uint64_t status:10;
+               uint64_t reserved_10_63:54;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_bist_cn52xx cn56xx;
        struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_bist_s cn61xx;
        struct cvmx_agl_gmx_bist_s cn63xx;
        struct cvmx_agl_gmx_bist_s cn63xxp1;
+       struct cvmx_agl_gmx_bist_s cn66xx;
+       struct cvmx_agl_gmx_bist_s cn68xx;
+       struct cvmx_agl_gmx_bist_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_drv_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_drv_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_49_63:15;
                uint64_t byp_en1:1;
                uint64_t reserved_45_47:3;
@@ -188,16 +255,39 @@ union cvmx_agl_gmx_drv_ctl {
                uint64_t pctl:5;
                uint64_t reserved_5_7:3;
                uint64_t nctl:5;
+#else
+               uint64_t nctl:5;
+               uint64_t reserved_5_7:3;
+               uint64_t pctl:5;
+               uint64_t reserved_13_15:3;
+               uint64_t byp_en:1;
+               uint64_t reserved_17_31:15;
+               uint64_t nctl1:5;
+               uint64_t reserved_37_39:3;
+               uint64_t pctl1:5;
+               uint64_t reserved_45_47:3;
+               uint64_t byp_en1:1;
+               uint64_t reserved_49_63:15;
+#endif
        } s;
        struct cvmx_agl_gmx_drv_ctl_s cn52xx;
        struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_drv_ctl_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_17_63:47;
                uint64_t byp_en:1;
                uint64_t reserved_13_15:3;
                uint64_t pctl:5;
                uint64_t reserved_5_7:3;
                uint64_t nctl:5;
+#else
+               uint64_t nctl:5;
+               uint64_t reserved_5_7:3;
+               uint64_t pctl:5;
+               uint64_t reserved_13_15:3;
+               uint64_t byp_en:1;
+               uint64_t reserved_17_63:47;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
 };
@@ -205,9 +295,15 @@ union cvmx_agl_gmx_drv_ctl {
 union cvmx_agl_gmx_inf_mode {
        uint64_t u64;
        struct cvmx_agl_gmx_inf_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_2_63:62;
                uint64_t en:1;
                uint64_t reserved_0_0:1;
+#else
+               uint64_t reserved_0_0:1;
+               uint64_t en:1;
+               uint64_t reserved_2_63:62;
+#endif
        } s;
        struct cvmx_agl_gmx_inf_mode_s cn52xx;
        struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
@@ -218,6 +314,7 @@ union cvmx_agl_gmx_inf_mode {
 union cvmx_agl_gmx_prtx_cfg {
        uint64_t u64;
        struct cvmx_agl_gmx_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_14_63:50;
                uint64_t tx_idle:1;
                uint64_t rx_idle:1;
@@ -231,8 +328,24 @@ union cvmx_agl_gmx_prtx_cfg {
                uint64_t duplex:1;
                uint64_t speed:1;
                uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t speed:1;
+               uint64_t duplex:1;
+               uint64_t slottime:1;
+               uint64_t rx_en:1;
+               uint64_t tx_en:1;
+               uint64_t burst:1;
+               uint64_t reserved_7_7:1;
+               uint64_t speed_msb:1;
+               uint64_t reserved_9_11:3;
+               uint64_t rx_idle:1;
+               uint64_t tx_idle:1;
+               uint64_t reserved_14_63:50;
+#endif
        } s;
        struct cvmx_agl_gmx_prtx_cfg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t tx_en:1;
                uint64_t rx_en:1;
@@ -240,139 +353,230 @@ union cvmx_agl_gmx_prtx_cfg {
                uint64_t duplex:1;
                uint64_t speed:1;
                uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t speed:1;
+               uint64_t duplex:1;
+               uint64_t slottime:1;
+               uint64_t rx_en:1;
+               uint64_t tx_en:1;
+               uint64_t reserved_6_63:58;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_prtx_cfg_s cn61xx;
        struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
        struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
+       struct cvmx_agl_gmx_prtx_cfg_s cn66xx;
+       struct cvmx_agl_gmx_prtx_cfg_s cn68xx;
+       struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam0 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t adr:64;
+#else
                uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam1 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t adr:64;
+#else
                uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam2 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t adr:64;
+#else
                uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam3 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t adr:64;
+#else
                uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam4 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t adr:64;
+#else
+               uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam5 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t adr:64;
+#else
+               uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam_en {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t en:8;
+#else
+               uint64_t en:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t cam_mode:1;
                uint64_t mcst:2;
                uint64_t bcst:1;
+#else
+               uint64_t bcst:1;
+               uint64_t mcst:2;
+               uint64_t cam_mode:1;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_decision {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_decision_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t cnt:5;
+#else
+               uint64_t cnt:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_decision_s cn52xx;
        struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_decision_s cn56xx;
        struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_decision_s cn61xx;
        struct cvmx_agl_gmx_rxx_decision_s cn63xx;
        struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_decision_s cn66xx;
+       struct cvmx_agl_gmx_rxx_decision_s cn68xx;
+       struct cvmx_agl_gmx_rxx_decision_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_chk {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_frm_chk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t niberr:1;
                uint64_t skperr:1;
@@ -384,8 +588,22 @@ union cvmx_agl_gmx_rxx_frm_chk {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t reserved_10_63:54;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t skperr:1;
                uint64_t rcverr:1;
@@ -396,17 +614,34 @@ union cvmx_agl_gmx_rxx_frm_chk {
                uint64_t maxerr:1;
                uint64_t reserved_1_1:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t reserved_1_1:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_63:55;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx;
        struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
        struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx;
+       struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx;
+       struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_frm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_13_63:51;
                uint64_t ptp_mode:1;
                uint64_t reserved_11_11:1;
@@ -421,8 +656,25 @@ union cvmx_agl_gmx_rxx_frm_ctl {
                uint64_t ctl_drp:1;
                uint64_t pre_strp:1;
                uint64_t pre_chk:1;
+#else
+               uint64_t pre_chk:1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t vlan_len:1;
+               uint64_t pad_len:1;
+               uint64_t pre_align:1;
+               uint64_t null_dis:1;
+               uint64_t reserved_11_11:1;
+               uint64_t ptp_mode:1;
+               uint64_t reserved_13_63:51;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t pre_align:1;
                uint64_t pad_len:1;
@@ -434,59 +686,104 @@ union cvmx_agl_gmx_rxx_frm_ctl {
                uint64_t ctl_drp:1;
                uint64_t pre_strp:1;
                uint64_t pre_chk:1;
+#else
+               uint64_t pre_chk:1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t vlan_len:1;
+               uint64_t pad_len:1;
+               uint64_t pre_align:1;
+               uint64_t reserved_10_63:54;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx;
        struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
        struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx;
+       struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx;
+       struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_max {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_frm_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t len:16;
+#else
+               uint64_t len:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
        struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
        struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_frm_max_s cn61xx;
        struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
        struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_frm_max_s cn66xx;
+       struct cvmx_agl_gmx_rxx_frm_max_s cn68xx;
+       struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_min {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_frm_min_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t len:16;
+#else
+               uint64_t len:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
        struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
        struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_frm_min_s cn61xx;
        struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
        struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_frm_min_s cn66xx;
+       struct cvmx_agl_gmx_rxx_frm_min_s cn68xx;
+       struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_ifg {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t ifg:4;
+#else
+               uint64_t ifg:4;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
        struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
        struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_ifg_s cn61xx;
        struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
        struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_ifg_s cn66xx;
+       struct cvmx_agl_gmx_rxx_ifg_s cn68xx;
+       struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_int_en {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t phy_dupx:1;
@@ -508,8 +805,32 @@ union cvmx_agl_gmx_rxx_int_en {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t reserved_16_18:3;
@@ -529,17 +850,43 @@ union cvmx_agl_gmx_rxx_int_en {
                uint64_t maxerr:1;
                uint64_t reserved_1_1:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t reserved_1_1:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_9:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t reserved_16_18:3;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_rxx_int_en_s cn61xx;
        struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
        struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_int_en_s cn66xx;
+       struct cvmx_agl_gmx_rxx_int_en_s cn68xx;
+       struct cvmx_agl_gmx_rxx_int_en_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_int_reg {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t phy_dupx:1;
@@ -561,8 +908,32 @@ union cvmx_agl_gmx_rxx_int_reg {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t reserved_16_18:3;
@@ -582,666 +953,1130 @@ union cvmx_agl_gmx_rxx_int_reg {
                uint64_t maxerr:1;
                uint64_t reserved_1_1:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t reserved_1_1:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_9:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t reserved_16_18:3;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_rxx_int_reg_s cn61xx;
        struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
        struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_int_reg_s cn66xx;
+       struct cvmx_agl_gmx_rxx_int_reg_s cn68xx;
+       struct cvmx_agl_gmx_rxx_int_reg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_jabber {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_jabber_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t cnt:16;
+#else
+               uint64_t cnt:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
        struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
        struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_jabber_s cn61xx;
        struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
        struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_jabber_s cn66xx;
+       struct cvmx_agl_gmx_rxx_jabber_s cn68xx;
+       struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_pause_drop_time {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t status:16;
+#else
+               uint64_t status:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx;
+       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx;
+       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_rx_inbnd {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_rx_inbnd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t duplex:1;
                uint64_t speed:2;
                uint64_t status:1;
+#else
+               uint64_t status:1;
+               uint64_t speed:2;
+               uint64_t duplex:1;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
+       struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx;
        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx;
+       struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx;
+       struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t rd_clr:1;
+#else
+               uint64_t rd_clr:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_octs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t cnt:48;
+#else
+               uint64_t cnt:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t cnt:48;
+#else
+               uint64_t cnt:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_dmac {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t cnt:48;
+#else
+               uint64_t cnt:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_drp {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t cnt:48;
+#else
+               uint64_t cnt:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_pkts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t cnt:32;
+#else
+               uint64_t cnt:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_bad {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t cnt:32;
+#else
+               uint64_t cnt:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t cnt:32;
+#else
+               uint64_t cnt:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_dmac {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t cnt:32;
+#else
+               uint64_t cnt:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_drp {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t cnt:32;
+#else
+               uint64_t cnt:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_udd_skp {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_udd_skp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t fcssel:1;
                uint64_t reserved_7_7:1;
                uint64_t len:7;
+#else
+               uint64_t len:7;
+               uint64_t reserved_7_7:1;
+               uint64_t fcssel:1;
+               uint64_t reserved_9_63:55;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx;
+       struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx;
+       struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_dropx {
        uint64_t u64;
        struct cvmx_agl_gmx_rx_bp_dropx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t mark:6;
+#else
+               uint64_t mark:6;
+               uint64_t reserved_6_63:58;
+#endif
        } s;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
+       struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
+       struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx;
+       struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx;
+       struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_offx {
        uint64_t u64;
        struct cvmx_agl_gmx_rx_bp_offx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t mark:6;
+#else
+               uint64_t mark:6;
+               uint64_t reserved_6_63:58;
+#endif
        } s;
        struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
        struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
        struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
        struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
+       struct cvmx_agl_gmx_rx_bp_offx_s cn61xx;
        struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
        struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
+       struct cvmx_agl_gmx_rx_bp_offx_s cn66xx;
+       struct cvmx_agl_gmx_rx_bp_offx_s cn68xx;
+       struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_onx {
        uint64_t u64;
        struct cvmx_agl_gmx_rx_bp_onx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t mark:9;
+#else
+               uint64_t mark:9;
+               uint64_t reserved_9_63:55;
+#endif
        } s;
        struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
        struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
        struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
        struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
+       struct cvmx_agl_gmx_rx_bp_onx_s cn61xx;
        struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
        struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
+       struct cvmx_agl_gmx_rx_bp_onx_s cn66xx;
+       struct cvmx_agl_gmx_rx_bp_onx_s cn68xx;
+       struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_prt_info {
        uint64_t u64;
        struct cvmx_agl_gmx_rx_prt_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_18_63:46;
                uint64_t drop:2;
                uint64_t reserved_2_15:14;
                uint64_t commit:2;
+#else
+               uint64_t commit:2;
+               uint64_t reserved_2_15:14;
+               uint64_t drop:2;
+               uint64_t reserved_18_63:46;
+#endif
        } s;
        struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
        struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
        struct cvmx_agl_gmx_rx_prt_info_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_17_63:47;
                uint64_t drop:1;
                uint64_t reserved_1_15:15;
                uint64_t commit:1;
+#else
+               uint64_t commit:1;
+               uint64_t reserved_1_15:15;
+               uint64_t drop:1;
+               uint64_t reserved_17_63:47;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+       struct cvmx_agl_gmx_rx_prt_info_s cn61xx;
        struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
        struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
+       struct cvmx_agl_gmx_rx_prt_info_s cn66xx;
+       struct cvmx_agl_gmx_rx_prt_info_s cn68xx;
+       struct cvmx_agl_gmx_rx_prt_info_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_tx_status {
        uint64_t u64;
        struct cvmx_agl_gmx_rx_tx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t tx:2;
                uint64_t reserved_2_3:2;
                uint64_t rx:2;
+#else
+               uint64_t rx:2;
+               uint64_t reserved_2_3:2;
+               uint64_t tx:2;
+               uint64_t reserved_6_63:58;
+#endif
        } s;
        struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
        struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
        struct cvmx_agl_gmx_rx_tx_status_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t tx:1;
                uint64_t reserved_1_3:3;
                uint64_t rx:1;
+#else
+               uint64_t rx:1;
+               uint64_t reserved_1_3:3;
+               uint64_t tx:1;
+               uint64_t reserved_5_63:59;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+       struct cvmx_agl_gmx_rx_tx_status_s cn61xx;
        struct cvmx_agl_gmx_rx_tx_status_s cn63xx;
        struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;
+       struct cvmx_agl_gmx_rx_tx_status_s cn66xx;
+       struct cvmx_agl_gmx_rx_tx_status_s cn68xx;
+       struct cvmx_agl_gmx_rx_tx_status_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_smacx {
        uint64_t u64;
        struct cvmx_agl_gmx_smacx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t smac:48;
+#else
+               uint64_t smac:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_smacx_s cn52xx;
        struct cvmx_agl_gmx_smacx_s cn52xxp1;
        struct cvmx_agl_gmx_smacx_s cn56xx;
        struct cvmx_agl_gmx_smacx_s cn56xxp1;
+       struct cvmx_agl_gmx_smacx_s cn61xx;
        struct cvmx_agl_gmx_smacx_s cn63xx;
        struct cvmx_agl_gmx_smacx_s cn63xxp1;
+       struct cvmx_agl_gmx_smacx_s cn66xx;
+       struct cvmx_agl_gmx_smacx_s cn68xx;
+       struct cvmx_agl_gmx_smacx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_stat_bp {
        uint64_t u64;
        struct cvmx_agl_gmx_stat_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_17_63:47;
                uint64_t bp:1;
                uint64_t cnt:16;
+#else
+               uint64_t cnt:16;
+               uint64_t bp:1;
+               uint64_t reserved_17_63:47;
+#endif
        } s;
        struct cvmx_agl_gmx_stat_bp_s cn52xx;
        struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
        struct cvmx_agl_gmx_stat_bp_s cn56xx;
        struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
+       struct cvmx_agl_gmx_stat_bp_s cn61xx;
        struct cvmx_agl_gmx_stat_bp_s cn63xx;
        struct cvmx_agl_gmx_stat_bp_s cn63xxp1;
+       struct cvmx_agl_gmx_stat_bp_s cn66xx;
+       struct cvmx_agl_gmx_stat_bp_s cn68xx;
+       struct cvmx_agl_gmx_stat_bp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_append {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_append_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t force_fcs:1;
                uint64_t fcs:1;
                uint64_t pad:1;
                uint64_t preamble:1;
+#else
+               uint64_t preamble:1;
+               uint64_t pad:1;
+               uint64_t fcs:1;
+               uint64_t force_fcs:1;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_append_s cn52xx;
        struct cvmx_agl_gmx_txx_append_s cn52xxp1;
        struct cvmx_agl_gmx_txx_append_s cn56xx;
        struct cvmx_agl_gmx_txx_append_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_append_s cn61xx;
        struct cvmx_agl_gmx_txx_append_s cn63xx;
        struct cvmx_agl_gmx_txx_append_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_append_s cn66xx;
+       struct cvmx_agl_gmx_txx_append_s cn68xx;
+       struct cvmx_agl_gmx_txx_append_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_clk {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_clk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t clk_cnt:6;
+#else
+               uint64_t clk_cnt:6;
+               uint64_t reserved_6_63:58;
+#endif
        } s;
+       struct cvmx_agl_gmx_txx_clk_s cn61xx;
        struct cvmx_agl_gmx_txx_clk_s cn63xx;
        struct cvmx_agl_gmx_txx_clk_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_clk_s cn66xx;
+       struct cvmx_agl_gmx_txx_clk_s cn68xx;
+       struct cvmx_agl_gmx_txx_clk_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_2_63:62;
                uint64_t xsdef_en:1;
                uint64_t xscol_en:1;
+#else
+               uint64_t xscol_en:1;
+               uint64_t xsdef_en:1;
+               uint64_t reserved_2_63:62;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_ctl_s cn52xx;
        struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_txx_ctl_s cn56xx;
        struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_ctl_s cn61xx;
        struct cvmx_agl_gmx_txx_ctl_s cn63xx;
        struct cvmx_agl_gmx_txx_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_ctl_s cn66xx;
+       struct cvmx_agl_gmx_txx_ctl_s cn68xx;
+       struct cvmx_agl_gmx_txx_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_min_pkt {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_min_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t min_size:8;
+#else
+               uint64_t min_size:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
        struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
        struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
        struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_min_pkt_s cn61xx;
        struct cvmx_agl_gmx_txx_min_pkt_s cn63xx;
        struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_min_pkt_s cn66xx;
+       struct cvmx_agl_gmx_txx_min_pkt_s cn68xx;
+       struct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_pkt_interval {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t interval:16;
+#else
+               uint64_t interval:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx;
        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx;
+       struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx;
+       struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_pkt_time {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_pause_pkt_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t time:16;
+#else
+               uint64_t time:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx;
        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx;
+       struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx;
+       struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_togo {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_pause_togo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t time:16;
+#else
+               uint64_t time:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
        struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
        struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
        struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_pause_togo_s cn61xx;
        struct cvmx_agl_gmx_txx_pause_togo_s cn63xx;
        struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_pause_togo_s cn66xx;
+       struct cvmx_agl_gmx_txx_pause_togo_s cn68xx;
+       struct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_zero {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_pause_zero_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t send:1;
+#else
+               uint64_t send:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
        struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
        struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
        struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_pause_zero_s cn61xx;
        struct cvmx_agl_gmx_txx_pause_zero_s cn63xx;
        struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_pause_zero_s cn66xx;
+       struct cvmx_agl_gmx_txx_pause_zero_s cn68xx;
+       struct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_soft_pause {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_soft_pause_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t time:16;
+#else
+               uint64_t time:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
        struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
        struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
        struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_soft_pause_s cn61xx;
        struct cvmx_agl_gmx_txx_soft_pause_s cn63xx;
        struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_soft_pause_s cn66xx;
+       struct cvmx_agl_gmx_txx_soft_pause_s cn68xx;
+       struct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat0 {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t xsdef:32;
                uint64_t xscol:32;
+#else
+               uint64_t xscol:32;
+               uint64_t xsdef:32;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stat0_s cn52xx;
        struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stat0_s cn56xx;
        struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stat0_s cn61xx;
        struct cvmx_agl_gmx_txx_stat0_s cn63xx;
        struct cvmx_agl_gmx_txx_stat0_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stat0_s cn66xx;
+       struct cvmx_agl_gmx_txx_stat0_s cn68xx;
+       struct cvmx_agl_gmx_txx_stat0_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat1 {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t scol:32;
                uint64_t mcol:32;
+#else
+               uint64_t mcol:32;
+               uint64_t scol:32;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stat1_s cn52xx;
        struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stat1_s cn56xx;
        struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stat1_s cn61xx;
        struct cvmx_agl_gmx_txx_stat1_s cn63xx;
        struct cvmx_agl_gmx_txx_stat1_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stat1_s cn66xx;
+       struct cvmx_agl_gmx_txx_stat1_s cn68xx;
+       struct cvmx_agl_gmx_txx_stat1_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat2 {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stat2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t octs:48;
+#else
+               uint64_t octs:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stat2_s cn52xx;
        struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stat2_s cn56xx;
        struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stat2_s cn61xx;
        struct cvmx_agl_gmx_txx_stat2_s cn63xx;
        struct cvmx_agl_gmx_txx_stat2_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stat2_s cn66xx;
+       struct cvmx_agl_gmx_txx_stat2_s cn68xx;
+       struct cvmx_agl_gmx_txx_stat2_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat3 {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stat3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t pkts:32;
+#else
+               uint64_t pkts:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stat3_s cn52xx;
        struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stat3_s cn56xx;
        struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stat3_s cn61xx;
        struct cvmx_agl_gmx_txx_stat3_s cn63xx;
        struct cvmx_agl_gmx_txx_stat3_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stat3_s cn66xx;
+       struct cvmx_agl_gmx_txx_stat3_s cn68xx;
+       struct cvmx_agl_gmx_txx_stat3_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat4 {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stat4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t hist1:32;
                uint64_t hist0:32;
+#else
+               uint64_t hist0:32;
+               uint64_t hist1:32;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stat4_s cn52xx;
        struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stat4_s cn56xx;
        struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stat4_s cn61xx;
        struct cvmx_agl_gmx_txx_stat4_s cn63xx;
        struct cvmx_agl_gmx_txx_stat4_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stat4_s cn66xx;
+       struct cvmx_agl_gmx_txx_stat4_s cn68xx;
+       struct cvmx_agl_gmx_txx_stat4_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat5 {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stat5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t hist3:32;
                uint64_t hist2:32;
+#else
+               uint64_t hist2:32;
+               uint64_t hist3:32;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stat5_s cn52xx;
        struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stat5_s cn56xx;
        struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stat5_s cn61xx;
        struct cvmx_agl_gmx_txx_stat5_s cn63xx;
        struct cvmx_agl_gmx_txx_stat5_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stat5_s cn66xx;
+       struct cvmx_agl_gmx_txx_stat5_s cn68xx;
+       struct cvmx_agl_gmx_txx_stat5_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat6 {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stat6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t hist5:32;
                uint64_t hist4:32;
+#else
+               uint64_t hist4:32;
+               uint64_t hist5:32;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stat6_s cn52xx;
        struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stat6_s cn56xx;
        struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stat6_s cn61xx;
        struct cvmx_agl_gmx_txx_stat6_s cn63xx;
        struct cvmx_agl_gmx_txx_stat6_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stat6_s cn66xx;
+       struct cvmx_agl_gmx_txx_stat6_s cn68xx;
+       struct cvmx_agl_gmx_txx_stat6_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat7 {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stat7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t hist7:32;
                uint64_t hist6:32;
+#else
+               uint64_t hist6:32;
+               uint64_t hist7:32;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stat7_s cn52xx;
        struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stat7_s cn56xx;
        struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stat7_s cn61xx;
        struct cvmx_agl_gmx_txx_stat7_s cn63xx;
        struct cvmx_agl_gmx_txx_stat7_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stat7_s cn66xx;
+       struct cvmx_agl_gmx_txx_stat7_s cn68xx;
+       struct cvmx_agl_gmx_txx_stat7_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat8 {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stat8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t mcst:32;
                uint64_t bcst:32;
+#else
+               uint64_t bcst:32;
+               uint64_t mcst:32;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stat8_s cn52xx;
        struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stat8_s cn56xx;
        struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stat8_s cn61xx;
        struct cvmx_agl_gmx_txx_stat8_s cn63xx;
        struct cvmx_agl_gmx_txx_stat8_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stat8_s cn66xx;
+       struct cvmx_agl_gmx_txx_stat8_s cn68xx;
+       struct cvmx_agl_gmx_txx_stat8_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat9 {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stat9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t undflw:32;
                uint64_t ctl:32;
+#else
+               uint64_t ctl:32;
+               uint64_t undflw:32;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stat9_s cn52xx;
        struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stat9_s cn56xx;
        struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stat9_s cn61xx;
        struct cvmx_agl_gmx_txx_stat9_s cn63xx;
        struct cvmx_agl_gmx_txx_stat9_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stat9_s cn66xx;
+       struct cvmx_agl_gmx_txx_stat9_s cn68xx;
+       struct cvmx_agl_gmx_txx_stat9_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stats_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t rd_clr:1;
+#else
+               uint64_t rd_clr:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
        struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
        struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_stats_ctl_s cn61xx;
        struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;
        struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_stats_ctl_s cn66xx;
+       struct cvmx_agl_gmx_txx_stats_ctl_s cn68xx;
+       struct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_thresh {
        uint64_t u64;
        struct cvmx_agl_gmx_txx_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t cnt:6;
+#else
+               uint64_t cnt:6;
+               uint64_t reserved_6_63:58;
+#endif
        } s;
        struct cvmx_agl_gmx_txx_thresh_s cn52xx;
        struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
        struct cvmx_agl_gmx_txx_thresh_s cn56xx;
        struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
+       struct cvmx_agl_gmx_txx_thresh_s cn61xx;
        struct cvmx_agl_gmx_txx_thresh_s cn63xx;
        struct cvmx_agl_gmx_txx_thresh_s cn63xxp1;
+       struct cvmx_agl_gmx_txx_thresh_s cn66xx;
+       struct cvmx_agl_gmx_txx_thresh_s cn68xx;
+       struct cvmx_agl_gmx_txx_thresh_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_bp {
        uint64_t u64;
        struct cvmx_agl_gmx_tx_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_2_63:62;
                uint64_t bp:2;
+#else
+               uint64_t bp:2;
+               uint64_t reserved_2_63:62;
+#endif
        } s;
        struct cvmx_agl_gmx_tx_bp_s cn52xx;
        struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
        struct cvmx_agl_gmx_tx_bp_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t bp:1;
+#else
+               uint64_t bp:1;
+               uint64_t reserved_1_63:63;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
+       struct cvmx_agl_gmx_tx_bp_s cn61xx;
        struct cvmx_agl_gmx_tx_bp_s cn63xx;
        struct cvmx_agl_gmx_tx_bp_s cn63xxp1;
+       struct cvmx_agl_gmx_tx_bp_s cn66xx;
+       struct cvmx_agl_gmx_tx_bp_s cn68xx;
+       struct cvmx_agl_gmx_tx_bp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_col_attempt {
        uint64_t u64;
        struct cvmx_agl_gmx_tx_col_attempt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t limit:5;
+#else
+               uint64_t limit:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
        struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
        struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
        struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
+       struct cvmx_agl_gmx_tx_col_attempt_s cn61xx;
        struct cvmx_agl_gmx_tx_col_attempt_s cn63xx;
        struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;
+       struct cvmx_agl_gmx_tx_col_attempt_s cn66xx;
+       struct cvmx_agl_gmx_tx_col_attempt_s cn68xx;
+       struct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_ifg {
        uint64_t u64;
        struct cvmx_agl_gmx_tx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t ifg2:4;
                uint64_t ifg1:4;
+#else
+               uint64_t ifg1:4;
+               uint64_t ifg2:4;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_agl_gmx_tx_ifg_s cn52xx;
        struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
        struct cvmx_agl_gmx_tx_ifg_s cn56xx;
        struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
+       struct cvmx_agl_gmx_tx_ifg_s cn61xx;
        struct cvmx_agl_gmx_tx_ifg_s cn63xx;
        struct cvmx_agl_gmx_tx_ifg_s cn63xxp1;
+       struct cvmx_agl_gmx_tx_ifg_s cn66xx;
+       struct cvmx_agl_gmx_tx_ifg_s cn68xx;
+       struct cvmx_agl_gmx_tx_ifg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_int_en {
        uint64_t u64;
        struct cvmx_agl_gmx_tx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_22_63:42;
                uint64_t ptp_lost:2;
                uint64_t reserved_18_19:2;
@@ -1254,8 +2089,23 @@ union cvmx_agl_gmx_tx_int_en {
                uint64_t undflw:2;
                uint64_t reserved_1_1:1;
                uint64_t pko_nxa:1;
+#else
+               uint64_t pko_nxa:1;
+               uint64_t reserved_1_1:1;
+               uint64_t undflw:2;
+               uint64_t reserved_4_7:4;
+               uint64_t xscol:2;
+               uint64_t reserved_10_11:2;
+               uint64_t xsdef:2;
+               uint64_t reserved_14_15:2;
+               uint64_t late_col:2;
+               uint64_t reserved_18_19:2;
+               uint64_t ptp_lost:2;
+               uint64_t reserved_22_63:42;
+#endif
        } s;
        struct cvmx_agl_gmx_tx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_18_63:46;
                uint64_t late_col:2;
                uint64_t reserved_14_15:2;
@@ -1266,9 +2116,22 @@ union cvmx_agl_gmx_tx_int_en {
                uint64_t undflw:2;
                uint64_t reserved_1_1:1;
                uint64_t pko_nxa:1;
+#else
+               uint64_t pko_nxa:1;
+               uint64_t reserved_1_1:1;
+               uint64_t undflw:2;
+               uint64_t reserved_4_7:4;
+               uint64_t xscol:2;
+               uint64_t reserved_10_11:2;
+               uint64_t xsdef:2;
+               uint64_t reserved_14_15:2;
+               uint64_t late_col:2;
+               uint64_t reserved_18_63:46;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_tx_int_en_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_17_63:47;
                uint64_t late_col:1;
                uint64_t reserved_13_15:3;
@@ -1279,15 +2142,32 @@ union cvmx_agl_gmx_tx_int_en {
                uint64_t undflw:1;
                uint64_t reserved_1_1:1;
                uint64_t pko_nxa:1;
+#else
+               uint64_t pko_nxa:1;
+               uint64_t reserved_1_1:1;
+               uint64_t undflw:1;
+               uint64_t reserved_3_7:5;
+               uint64_t xscol:1;
+               uint64_t reserved_9_11:3;
+               uint64_t xsdef:1;
+               uint64_t reserved_13_15:3;
+               uint64_t late_col:1;
+               uint64_t reserved_17_63:47;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
+       struct cvmx_agl_gmx_tx_int_en_s cn61xx;
        struct cvmx_agl_gmx_tx_int_en_s cn63xx;
        struct cvmx_agl_gmx_tx_int_en_s cn63xxp1;
+       struct cvmx_agl_gmx_tx_int_en_s cn66xx;
+       struct cvmx_agl_gmx_tx_int_en_s cn68xx;
+       struct cvmx_agl_gmx_tx_int_en_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_int_reg {
        uint64_t u64;
        struct cvmx_agl_gmx_tx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_22_63:42;
                uint64_t ptp_lost:2;
                uint64_t reserved_18_19:2;
@@ -1300,8 +2180,23 @@ union cvmx_agl_gmx_tx_int_reg {
                uint64_t undflw:2;
                uint64_t reserved_1_1:1;
                uint64_t pko_nxa:1;
+#else
+               uint64_t pko_nxa:1;
+               uint64_t reserved_1_1:1;
+               uint64_t undflw:2;
+               uint64_t reserved_4_7:4;
+               uint64_t xscol:2;
+               uint64_t reserved_10_11:2;
+               uint64_t xsdef:2;
+               uint64_t reserved_14_15:2;
+               uint64_t late_col:2;
+               uint64_t reserved_18_19:2;
+               uint64_t ptp_lost:2;
+               uint64_t reserved_22_63:42;
+#endif
        } s;
        struct cvmx_agl_gmx_tx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_18_63:46;
                uint64_t late_col:2;
                uint64_t reserved_14_15:2;
@@ -1312,9 +2207,22 @@ union cvmx_agl_gmx_tx_int_reg {
                uint64_t undflw:2;
                uint64_t reserved_1_1:1;
                uint64_t pko_nxa:1;
+#else
+               uint64_t pko_nxa:1;
+               uint64_t reserved_1_1:1;
+               uint64_t undflw:2;
+               uint64_t reserved_4_7:4;
+               uint64_t xscol:2;
+               uint64_t reserved_10_11:2;
+               uint64_t xsdef:2;
+               uint64_t reserved_14_15:2;
+               uint64_t late_col:2;
+               uint64_t reserved_18_63:46;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_tx_int_reg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_17_63:47;
                uint64_t late_col:1;
                uint64_t reserved_13_15:3;
@@ -1325,96 +2233,171 @@ union cvmx_agl_gmx_tx_int_reg {
                uint64_t undflw:1;
                uint64_t reserved_1_1:1;
                uint64_t pko_nxa:1;
+#else
+               uint64_t pko_nxa:1;
+               uint64_t reserved_1_1:1;
+               uint64_t undflw:1;
+               uint64_t reserved_3_7:5;
+               uint64_t xscol:1;
+               uint64_t reserved_9_11:3;
+               uint64_t xsdef:1;
+               uint64_t reserved_13_15:3;
+               uint64_t late_col:1;
+               uint64_t reserved_17_63:47;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+       struct cvmx_agl_gmx_tx_int_reg_s cn61xx;
        struct cvmx_agl_gmx_tx_int_reg_s cn63xx;
        struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;
+       struct cvmx_agl_gmx_tx_int_reg_s cn66xx;
+       struct cvmx_agl_gmx_tx_int_reg_s cn68xx;
+       struct cvmx_agl_gmx_tx_int_reg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_jam {
        uint64_t u64;
        struct cvmx_agl_gmx_tx_jam_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t jam:8;
+#else
+               uint64_t jam:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_agl_gmx_tx_jam_s cn52xx;
        struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
        struct cvmx_agl_gmx_tx_jam_s cn56xx;
        struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
+       struct cvmx_agl_gmx_tx_jam_s cn61xx;
        struct cvmx_agl_gmx_tx_jam_s cn63xx;
        struct cvmx_agl_gmx_tx_jam_s cn63xxp1;
+       struct cvmx_agl_gmx_tx_jam_s cn66xx;
+       struct cvmx_agl_gmx_tx_jam_s cn68xx;
+       struct cvmx_agl_gmx_tx_jam_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_lfsr {
        uint64_t u64;
        struct cvmx_agl_gmx_tx_lfsr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t lfsr:16;
+#else
+               uint64_t lfsr:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
        struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
        struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
        struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
+       struct cvmx_agl_gmx_tx_lfsr_s cn61xx;
        struct cvmx_agl_gmx_tx_lfsr_s cn63xx;
        struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;
+       struct cvmx_agl_gmx_tx_lfsr_s cn66xx;
+       struct cvmx_agl_gmx_tx_lfsr_s cn68xx;
+       struct cvmx_agl_gmx_tx_lfsr_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_ovr_bp {
        uint64_t u64;
        struct cvmx_agl_gmx_tx_ovr_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t en:2;
                uint64_t reserved_6_7:2;
                uint64_t bp:2;
                uint64_t reserved_2_3:2;
                uint64_t ign_full:2;
+#else
+               uint64_t ign_full:2;
+               uint64_t reserved_2_3:2;
+               uint64_t bp:2;
+               uint64_t reserved_6_7:2;
+               uint64_t en:2;
+               uint64_t reserved_10_63:54;
+#endif
        } s;
        struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
        struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
        struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t en:1;
                uint64_t reserved_5_7:3;
                uint64_t bp:1;
                uint64_t reserved_1_3:3;
                uint64_t ign_full:1;
+#else
+               uint64_t ign_full:1;
+               uint64_t reserved_1_3:3;
+               uint64_t bp:1;
+               uint64_t reserved_5_7:3;
+               uint64_t en:1;
+               uint64_t reserved_9_63:55;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
+       struct cvmx_agl_gmx_tx_ovr_bp_s cn61xx;
        struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;
        struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;
+       struct cvmx_agl_gmx_tx_ovr_bp_s cn66xx;
+       struct cvmx_agl_gmx_tx_ovr_bp_s cn68xx;
+       struct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_pause_pkt_dmac {
        uint64_t u64;
        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t dmac:48;
+#else
+               uint64_t dmac:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+       struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx;
        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
+       struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx;
+       struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx;
+       struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_pause_pkt_type {
        uint64_t u64;
        struct cvmx_agl_gmx_tx_pause_pkt_type_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t type:16;
+#else
+               uint64_t type:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+       struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx;
        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
+       struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx;
+       struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx;
+       struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1;
 };
 
 union cvmx_agl_prtx_ctl {
        uint64_t u64;
        struct cvmx_agl_prtx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t drv_byp:1;
                uint64_t reserved_62_62:1;
                uint64_t cmp_pctl:6;
@@ -1438,9 +2421,38 @@ union cvmx_agl_prtx_ctl {
                uint64_t enable:1;
                uint64_t clkrst:1;
                uint64_t mode:1;
+#else
+               uint64_t mode:1;
+               uint64_t clkrst:1;
+               uint64_t enable:1;
+               uint64_t comp:1;
+               uint64_t dllrst:1;
+               uint64_t reserved_5_7:3;
+               uint64_t clktx_set:5;
+               uint64_t reserved_13_14:2;
+               uint64_t clktx_byp:1;
+               uint64_t clkrx_set:5;
+               uint64_t reserved_21_22:2;
+               uint64_t clkrx_byp:1;
+               uint64_t clk_set:5;
+               uint64_t reserved_29_31:3;
+               uint64_t drv_nctl:6;
+               uint64_t reserved_38_39:2;
+               uint64_t drv_pctl:6;
+               uint64_t reserved_46_47:2;
+               uint64_t cmp_nctl:6;
+               uint64_t reserved_54_55:2;
+               uint64_t cmp_pctl:6;
+               uint64_t reserved_62_62:1;
+               uint64_t drv_byp:1;
+#endif
        } s;
+       struct cvmx_agl_prtx_ctl_s cn61xx;
        struct cvmx_agl_prtx_ctl_s cn63xx;
        struct cvmx_agl_prtx_ctl_s cn63xxp1;
+       struct cvmx_agl_prtx_ctl_s cn66xx;
+       struct cvmx_agl_prtx_ctl_s cn68xx;
+       struct cvmx_agl_prtx_ctl_s cn68xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h 
b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
index 91415a8..a1e21a3 100644
--- a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,64 +28,43 @@
 #ifndef __CVMX_ASXX_DEFS_H__
 #define __CVMX_ASXX_DEFS_H__
 
-#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 
0x8000000ull))
-#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 
0x8000000ull))
-#define CVMX_ASXX_INT_EN(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_INT_REG(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 
0x8000000ull))
-#define CVMX_ASXX_PRT_LOOP(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RLD_BYPASS(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RLD_COMP(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RLD_DATA_DRV(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RLD_SETTING(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_ASXX_RX_PRT_EN(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RX_WOL(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RX_WOL_MSK(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RX_WOL_POWOK(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_RX_WOL_SIG(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_ASXX_TX_COMP_BYP(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_ASXX_TX_PRT_EN(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 
0x8000000ull))
+#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000180ull))
+#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000188ull))
+#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + 
((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + 
((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_MII_RX_DAT_SET(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000190ull))
+#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + 
((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) 
+ ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + 
((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_DATA_DRV(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_SETTING(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 
0x1000000ull) * 8)
+#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) 
+ ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + 
((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) 
+ ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RX_WOL_POWOK(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) 
+ ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 
0x1000000ull) * 8)
+#define CVMX_ASXX_TX_COMP_BYP(block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) 
(CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 
0x1000000ull) * 8)
+#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) 
+ ((block_id) & 1) * 0x8000000ull)
 
 union cvmx_asxx_gmii_rx_clk_set {
        uint64_t u64;
        struct cvmx_asxx_gmii_rx_clk_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t setting:5;
+#else
+               uint64_t setting:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
        struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
@@ -95,8 +74,13 @@ union cvmx_asxx_gmii_rx_clk_set {
 union cvmx_asxx_gmii_rx_dat_set {
        uint64_t u64;
        struct cvmx_asxx_gmii_rx_dat_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t setting:5;
+#else
+               uint64_t setting:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
        struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
@@ -106,18 +90,34 @@ union cvmx_asxx_gmii_rx_dat_set {
 union cvmx_asxx_int_en {
        uint64_t u64;
        struct cvmx_asxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_12_63:52;
                uint64_t txpsh:4;
                uint64_t txpop:4;
                uint64_t ovrflw:4;
+#else
+               uint64_t ovrflw:4;
+               uint64_t txpop:4;
+               uint64_t txpsh:4;
+               uint64_t reserved_12_63:52;
+#endif
        } s;
        struct cvmx_asxx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_11_63:53;
                uint64_t txpsh:3;
                uint64_t reserved_7_7:1;
                uint64_t txpop:3;
                uint64_t reserved_3_3:1;
                uint64_t ovrflw:3;
+#else
+               uint64_t ovrflw:3;
+               uint64_t reserved_3_3:1;
+               uint64_t txpop:3;
+               uint64_t reserved_7_7:1;
+               uint64_t txpsh:3;
+               uint64_t reserved_11_63:53;
+#endif
        } cn30xx;
        struct cvmx_asxx_int_en_cn30xx cn31xx;
        struct cvmx_asxx_int_en_s cn38xx;
@@ -130,18 +130,34 @@ union cvmx_asxx_int_en {
 union cvmx_asxx_int_reg {
        uint64_t u64;
        struct cvmx_asxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_12_63:52;
                uint64_t txpsh:4;
                uint64_t txpop:4;
                uint64_t ovrflw:4;
+#else
+               uint64_t ovrflw:4;
+               uint64_t txpop:4;
+               uint64_t txpsh:4;
+               uint64_t reserved_12_63:52;
+#endif
        } s;
        struct cvmx_asxx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_11_63:53;
                uint64_t txpsh:3;
                uint64_t reserved_7_7:1;
                uint64_t txpop:3;
                uint64_t reserved_3_3:1;
                uint64_t ovrflw:3;
+#else
+               uint64_t ovrflw:3;
+               uint64_t reserved_3_3:1;
+               uint64_t txpop:3;
+               uint64_t reserved_7_7:1;
+               uint64_t txpsh:3;
+               uint64_t reserved_11_63:53;
+#endif
        } cn30xx;
        struct cvmx_asxx_int_reg_cn30xx cn31xx;
        struct cvmx_asxx_int_reg_s cn38xx;
@@ -154,8 +170,13 @@ union cvmx_asxx_int_reg {
 union cvmx_asxx_mii_rx_dat_set {
        uint64_t u64;
        struct cvmx_asxx_mii_rx_dat_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t setting:5;
+#else
+               uint64_t setting:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
        struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
@@ -164,15 +185,28 @@ union cvmx_asxx_mii_rx_dat_set {
 union cvmx_asxx_prt_loop {
        uint64_t u64;
        struct cvmx_asxx_prt_loop_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t ext_loop:4;
                uint64_t int_loop:4;
+#else
+               uint64_t int_loop:4;
+               uint64_t ext_loop:4;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_asxx_prt_loop_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_7_63:57;
                uint64_t ext_loop:3;
                uint64_t reserved_3_3:1;
                uint64_t int_loop:3;
+#else
+               uint64_t int_loop:3;
+               uint64_t reserved_3_3:1;
+               uint64_t ext_loop:3;
+               uint64_t reserved_7_63:57;
+#endif
        } cn30xx;
        struct cvmx_asxx_prt_loop_cn30xx cn31xx;
        struct cvmx_asxx_prt_loop_s cn38xx;
@@ -185,8 +219,13 @@ union cvmx_asxx_prt_loop {
 union cvmx_asxx_rld_bypass {
        uint64_t u64;
        struct cvmx_asxx_rld_bypass_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t bypass:1;
+#else
+               uint64_t bypass:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
        struct cvmx_asxx_rld_bypass_s cn38xx;
        struct cvmx_asxx_rld_bypass_s cn38xxp2;
@@ -197,8 +236,13 @@ union cvmx_asxx_rld_bypass {
 union cvmx_asxx_rld_bypass_setting {
        uint64_t u64;
        struct cvmx_asxx_rld_bypass_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t setting:5;
+#else
+               uint64_t setting:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_asxx_rld_bypass_setting_s cn38xx;
        struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
@@ -209,14 +253,26 @@ union cvmx_asxx_rld_bypass_setting {
 union cvmx_asxx_rld_comp {
        uint64_t u64;
        struct cvmx_asxx_rld_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t pctl:5;
                uint64_t nctl:4;
+#else
+               uint64_t nctl:4;
+               uint64_t pctl:5;
+               uint64_t reserved_9_63:55;
+#endif
        } s;
        struct cvmx_asxx_rld_comp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t pctl:4;
                uint64_t nctl:4;
+#else
+               uint64_t nctl:4;
+               uint64_t pctl:4;
+               uint64_t reserved_8_63:56;
+#endif
        } cn38xx;
        struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
        struct cvmx_asxx_rld_comp_s cn58xx;
@@ -226,9 +282,15 @@ union cvmx_asxx_rld_comp {
 union cvmx_asxx_rld_data_drv {
        uint64_t u64;
        struct cvmx_asxx_rld_data_drv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t pctl:4;
                uint64_t nctl:4;
+#else
+               uint64_t nctl:4;
+               uint64_t pctl:4;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_asxx_rld_data_drv_s cn38xx;
        struct cvmx_asxx_rld_data_drv_s cn38xxp2;
@@ -239,8 +301,13 @@ union cvmx_asxx_rld_data_drv {
 union cvmx_asxx_rld_fcram_mode {
        uint64_t u64;
        struct cvmx_asxx_rld_fcram_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t mode:1;
+#else
+               uint64_t mode:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
        struct cvmx_asxx_rld_fcram_mode_s cn38xx;
        struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
@@ -249,8 +316,13 @@ union cvmx_asxx_rld_fcram_mode {
 union cvmx_asxx_rld_nctl_strong {
        uint64_t u64;
        struct cvmx_asxx_rld_nctl_strong_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t nctl:5;
+#else
+               uint64_t nctl:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_asxx_rld_nctl_strong_s cn38xx;
        struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
@@ -261,8 +333,13 @@ union cvmx_asxx_rld_nctl_strong {
 union cvmx_asxx_rld_nctl_weak {
        uint64_t u64;
        struct cvmx_asxx_rld_nctl_weak_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t nctl:5;
+#else
+               uint64_t nctl:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_asxx_rld_nctl_weak_s cn38xx;
        struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
@@ -273,8 +350,13 @@ union cvmx_asxx_rld_nctl_weak {
 union cvmx_asxx_rld_pctl_strong {
        uint64_t u64;
        struct cvmx_asxx_rld_pctl_strong_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t pctl:5;
+#else
+               uint64_t pctl:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_asxx_rld_pctl_strong_s cn38xx;
        struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
@@ -285,8 +367,13 @@ union cvmx_asxx_rld_pctl_strong {
 union cvmx_asxx_rld_pctl_weak {
        uint64_t u64;
        struct cvmx_asxx_rld_pctl_weak_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t pctl:5;
+#else
+               uint64_t pctl:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_asxx_rld_pctl_weak_s cn38xx;
        struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
@@ -297,16 +384,30 @@ union cvmx_asxx_rld_pctl_weak {
 union cvmx_asxx_rld_setting {
        uint64_t u64;
        struct cvmx_asxx_rld_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_13_63:51;
                uint64_t dfaset:5;
                uint64_t dfalag:1;
                uint64_t dfalead:1;
                uint64_t dfalock:1;
                uint64_t setting:5;
+#else
+               uint64_t setting:5;
+               uint64_t dfalock:1;
+               uint64_t dfalead:1;
+               uint64_t dfalag:1;
+               uint64_t dfaset:5;
+               uint64_t reserved_13_63:51;
+#endif
        } s;
        struct cvmx_asxx_rld_setting_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t setting:5;
+#else
+               uint64_t setting:5;
+               uint64_t reserved_5_63:59;
+#endif
        } cn38xx;
        struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
        struct cvmx_asxx_rld_setting_s cn58xx;
@@ -316,8 +417,13 @@ union cvmx_asxx_rld_setting {
 union cvmx_asxx_rx_clk_setx {
        uint64_t u64;
        struct cvmx_asxx_rx_clk_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t setting:5;
+#else
+               uint64_t setting:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_asxx_rx_clk_setx_s cn30xx;
        struct cvmx_asxx_rx_clk_setx_s cn31xx;
@@ -331,12 +437,22 @@ union cvmx_asxx_rx_clk_setx {
 union cvmx_asxx_rx_prt_en {
        uint64_t u64;
        struct cvmx_asxx_rx_prt_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t prt_en:4;
+#else
+               uint64_t prt_en:4;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
        struct cvmx_asxx_rx_prt_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_3_63:61;
                uint64_t prt_en:3;
+#else
+               uint64_t prt_en:3;
+               uint64_t reserved_3_63:61;
+#endif
        } cn30xx;
        struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
        struct cvmx_asxx_rx_prt_en_s cn38xx;
@@ -349,9 +465,15 @@ union cvmx_asxx_rx_prt_en {
 union cvmx_asxx_rx_wol {
        uint64_t u64;
        struct cvmx_asxx_rx_wol_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_2_63:62;
                uint64_t status:1;
                uint64_t enable:1;
+#else
+               uint64_t enable:1;
+               uint64_t status:1;
+               uint64_t reserved_2_63:62;
+#endif
        } s;
        struct cvmx_asxx_rx_wol_s cn38xx;
        struct cvmx_asxx_rx_wol_s cn38xxp2;
@@ -360,7 +482,11 @@ union cvmx_asxx_rx_wol {
 union cvmx_asxx_rx_wol_msk {
        uint64_t u64;
        struct cvmx_asxx_rx_wol_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t msk:64;
+#else
                uint64_t msk:64;
+#endif
        } s;
        struct cvmx_asxx_rx_wol_msk_s cn38xx;
        struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
@@ -369,8 +495,13 @@ union cvmx_asxx_rx_wol_msk {
 union cvmx_asxx_rx_wol_powok {
        uint64_t u64;
        struct cvmx_asxx_rx_wol_powok_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t powerok:1;
+#else
+               uint64_t powerok:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
        struct cvmx_asxx_rx_wol_powok_s cn38xx;
        struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
@@ -379,8 +510,13 @@ union cvmx_asxx_rx_wol_powok {
 union cvmx_asxx_rx_wol_sig {
        uint64_t u64;
        struct cvmx_asxx_rx_wol_sig_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t sig:32;
+#else
+               uint64_t sig:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_asxx_rx_wol_sig_s cn38xx;
        struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
@@ -389,8 +525,13 @@ union cvmx_asxx_rx_wol_sig {
 union cvmx_asxx_tx_clk_setx {
        uint64_t u64;
        struct cvmx_asxx_tx_clk_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t setting:5;
+#else
+               uint64_t setting:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_asxx_tx_clk_setx_s cn30xx;
        struct cvmx_asxx_tx_clk_setx_s cn31xx;
@@ -404,34 +545,67 @@ union cvmx_asxx_tx_clk_setx {
 union cvmx_asxx_tx_comp_byp {
        uint64_t u64;
        struct cvmx_asxx_tx_comp_byp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_0_63:64;
+#else
                uint64_t reserved_0_63:64;
+#endif
        } s;
        struct cvmx_asxx_tx_comp_byp_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t bypass:1;
                uint64_t pctl:4;
                uint64_t nctl:4;
+#else
+               uint64_t nctl:4;
+               uint64_t pctl:4;
+               uint64_t bypass:1;
+               uint64_t reserved_9_63:55;
+#endif
        } cn30xx;
        struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
        struct cvmx_asxx_tx_comp_byp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t pctl:4;
                uint64_t nctl:4;
+#else
+               uint64_t nctl:4;
+               uint64_t pctl:4;
+               uint64_t reserved_8_63:56;
+#endif
        } cn38xx;
        struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
        struct cvmx_asxx_tx_comp_byp_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_17_63:47;
                uint64_t bypass:1;
                uint64_t reserved_13_15:3;
                uint64_t pctl:5;
                uint64_t reserved_5_7:3;
                uint64_t nctl:5;
+#else
+               uint64_t nctl:5;
+               uint64_t reserved_5_7:3;
+               uint64_t pctl:5;
+               uint64_t reserved_13_15:3;
+               uint64_t bypass:1;
+               uint64_t reserved_17_63:47;
+#endif
        } cn50xx;
        struct cvmx_asxx_tx_comp_byp_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_13_63:51;
                uint64_t pctl:5;
                uint64_t reserved_5_7:3;
                uint64_t nctl:5;
+#else
+               uint64_t nctl:5;
+               uint64_t reserved_5_7:3;
+               uint64_t pctl:5;
+               uint64_t reserved_13_63:51;
+#endif
        } cn58xx;
        struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
 };
@@ -439,12 +613,22 @@ union cvmx_asxx_tx_comp_byp {
 union cvmx_asxx_tx_hi_waterx {
        uint64_t u64;
        struct cvmx_asxx_tx_hi_waterx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t mark:4;
+#else
+               uint64_t mark:4;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
        struct cvmx_asxx_tx_hi_waterx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_3_63:61;
                uint64_t mark:3;
+#else
+               uint64_t mark:3;
+               uint64_t reserved_3_63:61;
+#endif
        } cn30xx;
        struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
        struct cvmx_asxx_tx_hi_waterx_s cn38xx;
@@ -457,12 +641,22 @@ union cvmx_asxx_tx_hi_waterx {
 union cvmx_asxx_tx_prt_en {
        uint64_t u64;
        struct cvmx_asxx_tx_prt_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t prt_en:4;
+#else
+               uint64_t prt_en:4;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
        struct cvmx_asxx_tx_prt_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_3_63:61;
                uint64_t prt_en:3;
+#else
+               uint64_t prt_en:3;
+               uint64_t reserved_3_63:61;
+#endif
        } cn30xx;
        struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
        struct cvmx_asxx_tx_prt_en_s cn38xx;
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h 
b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
index 27cead3..0dd0e40 100644
--- a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -31,6 +31,18 @@
 #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
 #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
 #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
+#define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + 
((offset) & 1) * 8)
+#define CVMX_CIU_EN2_IOX_INT_W1C(offset) 
(CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8)
+#define CVMX_CIU_EN2_IOX_INT_W1S(offset) 
(CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8)
+#define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + 
((offset) & 15) * 8)
+#define CVMX_CIU_EN2_PPX_IP2_W1C(offset) 
(CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_EN2_PPX_IP2_W1S(offset) 
(CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + 
((offset) & 15) * 8)
+#define CVMX_CIU_EN2_PPX_IP3_W1C(offset) 
(CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_EN2_PPX_IP3_W1S(offset) 
(CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + 
((offset) & 15) * 8)
+#define CVMX_CIU_EN2_PPX_IP4_W1C(offset) 
(CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_EN2_PPX_IP4_W1S(offset) 
(CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8)
 #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
 #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
 #define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
@@ -50,60 +62,222 @@
 #define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + 
((offset) & 15) * 8)
 #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
 #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
-#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + 
((offset) & 15) * 8)
-#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + 
((offset) & 15) * 8)
+static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8;
+       }
+       return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
+}
+
+static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8;
+       }
+       return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
+}
+
 #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
 #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
+#define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
 #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
-#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + 
((offset) & 15) * 8)
+static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8;
+       }
+       return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
+}
+
 #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
 #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
 #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
 #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
+#define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull))
+#define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull))
 #define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
 #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
 #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
 #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
 #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
 #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
+#define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull))
+#define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
 #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
-#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + 
((offset) & 3) * 8)
-#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + 
((offset) & 15) * 8)
+#define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) 
+ ((offset) & 1) * 8)
+#define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) 
+ ((offset) & 15) * 8)
+#define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) 
+ ((offset) & 15) * 8)
+#define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) 
+ ((offset) & 15) * 8)
+#define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) 
+ ((offset) & 1) * 8)
+#define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) 
+ ((offset) & 15) * 8)
+#define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) 
+ ((offset) & 15) * 8)
+#define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) 
+ ((offset) & 15) * 8)
+#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + 
((offset) & 15) * 8)
+#define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull))
+static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8;
+       }
+       return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
+}
 
 union cvmx_ciu_bist {
        uint64_t u64;
        struct cvmx_ciu_bist_s {
-               uint64_t reserved_5_63:59;
-               uint64_t bist:5;
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_7_63:57;
+               uint64_t bist:7;
+#else
+               uint64_t bist:7;
+               uint64_t reserved_7_63:57;
+#endif
        } s;
        struct cvmx_ciu_bist_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t bist:4;
+#else
+               uint64_t bist:4;
+               uint64_t reserved_4_63:60;
+#endif
        } cn30xx;
        struct cvmx_ciu_bist_cn30xx cn31xx;
        struct cvmx_ciu_bist_cn30xx cn38xx;
        struct cvmx_ciu_bist_cn30xx cn38xxp2;
        struct cvmx_ciu_bist_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_2_63:62;
                uint64_t bist:2;
+#else
+               uint64_t bist:2;
+               uint64_t reserved_2_63:62;
+#endif
        } cn50xx;
        struct cvmx_ciu_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_3_63:61;
                uint64_t bist:3;
+#else
+               uint64_t bist:3;
+               uint64_t reserved_3_63:61;
+#endif
        } cn52xx;
        struct cvmx_ciu_bist_cn52xx cn52xxp1;
        struct cvmx_ciu_bist_cn30xx cn56xx;
        struct cvmx_ciu_bist_cn30xx cn56xxp1;
        struct cvmx_ciu_bist_cn30xx cn58xx;
        struct cvmx_ciu_bist_cn30xx cn58xxp1;
-       struct cvmx_ciu_bist_s cn63xx;
-       struct cvmx_ciu_bist_s cn63xxp1;
+       struct cvmx_ciu_bist_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_6_63:58;
+               uint64_t bist:6;
+#else
+               uint64_t bist:6;
+               uint64_t reserved_6_63:58;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_bist_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_5_63:59;
+               uint64_t bist:5;
+#else
+               uint64_t bist:5;
+               uint64_t reserved_5_63:59;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_bist_cn63xx cn63xxp1;
+       struct cvmx_ciu_bist_cn61xx cn66xx;
+       struct cvmx_ciu_bist_s cn68xx;
+       struct cvmx_ciu_bist_s cn68xxp1;
+       struct cvmx_ciu_bist_cn61xx cnf71xx;
 };
 
 union cvmx_ciu_block_int {
        uint64_t u64;
        struct cvmx_ciu_block_int_s {
-               uint64_t reserved_43_63:21;
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_62_63:2;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_43_59:17;
                uint64_t ptp:1;
                uint64_t dpi:1;
                uint64_t dfm:1;
@@ -117,7 +291,8 @@ union cvmx_ciu_block_int {
                uint64_t reserved_27_27:1;
                uint64_t pem1:1;
                uint64_t pem0:1;
-               uint64_t reserved_23_24:2;
+               uint64_t reserved_24_24:1;
+               uint64_t asxpcs1:1;
                uint64_t asxpcs0:1;
                uint64_t reserved_21_21:1;
                uint64_t pip:1;
@@ -137,966 +312,8360 @@ union cvmx_ciu_block_int {
                uint64_t fpa:1;
                uint64_t key:1;
                uint64_t sli:1;
-               uint64_t reserved_2_2:1;
+               uint64_t gmx1:1;
                uint64_t gmx0:1;
                uint64_t mio:1;
-       } s;
-       struct cvmx_ciu_block_int_s cn63xx;
-       struct cvmx_ciu_block_int_s cn63xxp1;
-};
-
-union cvmx_ciu_dint {
-       uint64_t u64;
-       struct cvmx_ciu_dint_s {
-               uint64_t reserved_16_63:48;
-               uint64_t dint:16;
-       } s;
-       struct cvmx_ciu_dint_cn30xx {
-               uint64_t reserved_1_63:63;
-               uint64_t dint:1;
-       } cn30xx;
-       struct cvmx_ciu_dint_cn31xx {
-               uint64_t reserved_2_63:62;
-               uint64_t dint:2;
-       } cn31xx;
-       struct cvmx_ciu_dint_s cn38xx;
-       struct cvmx_ciu_dint_s cn38xxp2;
-       struct cvmx_ciu_dint_cn31xx cn50xx;
-       struct cvmx_ciu_dint_cn52xx {
-               uint64_t reserved_4_63:60;
-               uint64_t dint:4;
-       } cn52xx;
-       struct cvmx_ciu_dint_cn52xx cn52xxp1;
-       struct cvmx_ciu_dint_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t dint:12;
-       } cn56xx;
-       struct cvmx_ciu_dint_cn56xx cn56xxp1;
-       struct cvmx_ciu_dint_s cn58xx;
-       struct cvmx_ciu_dint_s cn58xxp1;
-       struct cvmx_ciu_dint_cn63xx {
-               uint64_t reserved_6_63:58;
-               uint64_t dint:6;
-       } cn63xx;
-       struct cvmx_ciu_dint_cn63xx cn63xxp1;
-};
-
-union cvmx_ciu_fuse {
-       uint64_t u64;
-       struct cvmx_ciu_fuse_s {
-               uint64_t reserved_16_63:48;
-               uint64_t fuse:16;
-       } s;
-       struct cvmx_ciu_fuse_cn30xx {
-               uint64_t reserved_1_63:63;
-               uint64_t fuse:1;
-       } cn30xx;
-       struct cvmx_ciu_fuse_cn31xx {
-               uint64_t reserved_2_63:62;
-               uint64_t fuse:2;
-       } cn31xx;
-       struct cvmx_ciu_fuse_s cn38xx;
-       struct cvmx_ciu_fuse_s cn38xxp2;
-       struct cvmx_ciu_fuse_cn31xx cn50xx;
-       struct cvmx_ciu_fuse_cn52xx {
-               uint64_t reserved_4_63:60;
-               uint64_t fuse:4;
-       } cn52xx;
-       struct cvmx_ciu_fuse_cn52xx cn52xxp1;
-       struct cvmx_ciu_fuse_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t fuse:12;
-       } cn56xx;
-       struct cvmx_ciu_fuse_cn56xx cn56xxp1;
-       struct cvmx_ciu_fuse_s cn58xx;
-       struct cvmx_ciu_fuse_s cn58xxp1;
-       struct cvmx_ciu_fuse_cn63xx {
-               uint64_t reserved_6_63:58;
-               uint64_t fuse:6;
-       } cn63xx;
-       struct cvmx_ciu_fuse_cn63xx cn63xxp1;
-};
-
-union cvmx_ciu_gstop {
-       uint64_t u64;
-       struct cvmx_ciu_gstop_s {
-               uint64_t reserved_1_63:63;
-               uint64_t gstop:1;
-       } s;
-       struct cvmx_ciu_gstop_s cn30xx;
-       struct cvmx_ciu_gstop_s cn31xx;
-       struct cvmx_ciu_gstop_s cn38xx;
-       struct cvmx_ciu_gstop_s cn38xxp2;
-       struct cvmx_ciu_gstop_s cn50xx;
-       struct cvmx_ciu_gstop_s cn52xx;
-       struct cvmx_ciu_gstop_s cn52xxp1;
-       struct cvmx_ciu_gstop_s cn56xx;
-       struct cvmx_ciu_gstop_s cn56xxp1;
-       struct cvmx_ciu_gstop_s cn58xx;
-       struct cvmx_ciu_gstop_s cn58xxp1;
-       struct cvmx_ciu_gstop_s cn63xx;
-       struct cvmx_ciu_gstop_s cn63xxp1;
-};
-
-union cvmx_ciu_intx_en0 {
-       uint64_t u64;
-       struct cvmx_ciu_intx_en0_s {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t mpi:1;
-               uint64_t pcm:1;
+#else
+               uint64_t mio:1;
+               uint64_t gmx0:1;
+               uint64_t gmx1:1;
+               uint64_t sli:1;
+               uint64_t key:1;
+               uint64_t fpa:1;
+               uint64_t dfa:1;
+               uint64_t zip:1;
+               uint64_t reserved_8_8:1;
+               uint64_t ipd:1;
+               uint64_t pko:1;
+               uint64_t tim:1;
+               uint64_t pow:1;
                uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
+               uint64_t rad:1;
+               uint64_t reserved_15_15:1;
+               uint64_t l2c:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_18_19:2;
+               uint64_t pip:1;
+               uint64_t reserved_21_21:1;
+               uint64_t asxpcs0:1;
+               uint64_t asxpcs1:1;
+               uint64_t reserved_24_24:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_27_27:1;
+               uint64_t agl:1;
+               uint64_t reserved_29_29:1;
+               uint64_t iob:1;
+               uint64_t reserved_31_31:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfm:1;
+               uint64_t dpi:1;
+               uint64_t ptp:1;
+               uint64_t reserved_43_59:17;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_63:2;
+#endif
        } s;
-       struct cvmx_ciu_intx_en0_cn30xx {
-               uint64_t reserved_59_63:5;
-               uint64_t mpi:1;
-               uint64_t pcm:1;
+       struct cvmx_ciu_block_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_43_63:21;
+               uint64_t ptp:1;
+               uint64_t dpi:1;
+               uint64_t reserved_31_40:10;
+               uint64_t iob:1;
+               uint64_t reserved_29_29:1;
+               uint64_t agl:1;
+               uint64_t reserved_27_27:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t reserved_24_24:1;
+               uint64_t asxpcs1:1;
+               uint64_t asxpcs0:1;
+               uint64_t reserved_21_21:1;
+               uint64_t pip:1;
+               uint64_t reserved_18_19:2;
+               uint64_t lmc0:1;
+               uint64_t l2c:1;
+               uint64_t reserved_15_15:1;
+               uint64_t rad:1;
                uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t reserved_47_47:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn30xx;
-       struct cvmx_ciu_intx_en0_cn31xx {
-               uint64_t reserved_59_63:5;
-               uint64_t mpi:1;
-               uint64_t pcm:1;
+               uint64_t pow:1;
+               uint64_t tim:1;
+               uint64_t pko:1;
+               uint64_t ipd:1;
+               uint64_t reserved_8_8:1;
+               uint64_t zip:1;
+               uint64_t dfa:1;
+               uint64_t fpa:1;
+               uint64_t key:1;
+               uint64_t sli:1;
+               uint64_t gmx1:1;
+               uint64_t gmx0:1;
+               uint64_t mio:1;
+#else
+               uint64_t mio:1;
+               uint64_t gmx0:1;
+               uint64_t gmx1:1;
+               uint64_t sli:1;
+               uint64_t key:1;
+               uint64_t fpa:1;
+               uint64_t dfa:1;
+               uint64_t zip:1;
+               uint64_t reserved_8_8:1;
+               uint64_t ipd:1;
+               uint64_t pko:1;
+               uint64_t tim:1;
+               uint64_t pow:1;
                uint64_t usb:1;
+               uint64_t rad:1;
+               uint64_t reserved_15_15:1;
+               uint64_t l2c:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_18_19:2;
+               uint64_t pip:1;
+               uint64_t reserved_21_21:1;
+               uint64_t asxpcs0:1;
+               uint64_t asxpcs1:1;
+               uint64_t reserved_24_24:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_27_27:1;
+               uint64_t agl:1;
+               uint64_t reserved_29_29:1;
+               uint64_t iob:1;
+               uint64_t reserved_31_40:10;
+               uint64_t dpi:1;
+               uint64_t ptp:1;
+               uint64_t reserved_43_63:21;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_block_int_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_43_63:21;
+               uint64_t ptp:1;
+               uint64_t dpi:1;
+               uint64_t dfm:1;
+               uint64_t reserved_34_39:6;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_31_31:1;
+               uint64_t iob:1;
+               uint64_t reserved_29_29:1;
+               uint64_t agl:1;
+               uint64_t reserved_27_27:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t reserved_23_24:2;
+               uint64_t asxpcs0:1;
+               uint64_t reserved_21_21:1;
+               uint64_t pip:1;
+               uint64_t reserved_18_19:2;
+               uint64_t lmc0:1;
+               uint64_t l2c:1;
+               uint64_t reserved_15_15:1;
+               uint64_t rad:1;
+               uint64_t usb:1;
+               uint64_t pow:1;
+               uint64_t tim:1;
+               uint64_t pko:1;
+               uint64_t ipd:1;
+               uint64_t reserved_8_8:1;
+               uint64_t zip:1;
+               uint64_t dfa:1;
+               uint64_t fpa:1;
+               uint64_t key:1;
+               uint64_t sli:1;
+               uint64_t reserved_2_2:1;
+               uint64_t gmx0:1;
+               uint64_t mio:1;
+#else
+               uint64_t mio:1;
+               uint64_t gmx0:1;
+               uint64_t reserved_2_2:1;
+               uint64_t sli:1;
+               uint64_t key:1;
+               uint64_t fpa:1;
+               uint64_t dfa:1;
+               uint64_t zip:1;
+               uint64_t reserved_8_8:1;
+               uint64_t ipd:1;
+               uint64_t pko:1;
+               uint64_t tim:1;
+               uint64_t pow:1;
+               uint64_t usb:1;
+               uint64_t rad:1;
+               uint64_t reserved_15_15:1;
+               uint64_t l2c:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_18_19:2;
+               uint64_t pip:1;
+               uint64_t reserved_21_21:1;
+               uint64_t asxpcs0:1;
+               uint64_t reserved_23_24:2;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_27_27:1;
+               uint64_t agl:1;
+               uint64_t reserved_29_29:1;
+               uint64_t iob:1;
+               uint64_t reserved_31_31:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfm:1;
+               uint64_t dpi:1;
+               uint64_t ptp:1;
+               uint64_t reserved_43_63:21;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_block_int_cn63xx cn63xxp1;
+       struct cvmx_ciu_block_int_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_62_63:2;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_43_59:17;
+               uint64_t ptp:1;
+               uint64_t dpi:1;
+               uint64_t dfm:1;
+               uint64_t reserved_33_39:7;
+               uint64_t srio0:1;
+               uint64_t reserved_31_31:1;
+               uint64_t iob:1;
+               uint64_t reserved_29_29:1;
+               uint64_t agl:1;
+               uint64_t reserved_27_27:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t reserved_24_24:1;
+               uint64_t asxpcs1:1;
+               uint64_t asxpcs0:1;
+               uint64_t reserved_21_21:1;
+               uint64_t pip:1;
+               uint64_t reserved_18_19:2;
+               uint64_t lmc0:1;
+               uint64_t l2c:1;
+               uint64_t reserved_15_15:1;
+               uint64_t rad:1;
+               uint64_t usb:1;
+               uint64_t pow:1;
+               uint64_t tim:1;
+               uint64_t pko:1;
+               uint64_t ipd:1;
+               uint64_t reserved_8_8:1;
+               uint64_t zip:1;
+               uint64_t dfa:1;
+               uint64_t fpa:1;
+               uint64_t key:1;
+               uint64_t sli:1;
+               uint64_t gmx1:1;
+               uint64_t gmx0:1;
+               uint64_t mio:1;
+#else
+               uint64_t mio:1;
+               uint64_t gmx0:1;
+               uint64_t gmx1:1;
+               uint64_t sli:1;
+               uint64_t key:1;
+               uint64_t fpa:1;
+               uint64_t dfa:1;
+               uint64_t zip:1;
+               uint64_t reserved_8_8:1;
+               uint64_t ipd:1;
+               uint64_t pko:1;
+               uint64_t tim:1;
+               uint64_t pow:1;
+               uint64_t usb:1;
+               uint64_t rad:1;
+               uint64_t reserved_15_15:1;
+               uint64_t l2c:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_18_19:2;
+               uint64_t pip:1;
+               uint64_t reserved_21_21:1;
+               uint64_t asxpcs0:1;
+               uint64_t asxpcs1:1;
+               uint64_t reserved_24_24:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_27_27:1;
+               uint64_t agl:1;
+               uint64_t reserved_29_29:1;
+               uint64_t iob:1;
+               uint64_t reserved_31_31:1;
+               uint64_t srio0:1;
+               uint64_t reserved_33_39:7;
+               uint64_t dfm:1;
+               uint64_t dpi:1;
+               uint64_t ptp:1;
+               uint64_t reserved_43_59:17;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_63:2;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_block_int_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_43_63:21;
+               uint64_t ptp:1;
+               uint64_t dpi:1;
+               uint64_t reserved_31_40:10;
+               uint64_t iob:1;
+               uint64_t reserved_27_29:3;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t reserved_23_24:2;
+               uint64_t asxpcs0:1;
+               uint64_t reserved_21_21:1;
+               uint64_t pip:1;
+               uint64_t reserved_18_19:2;
+               uint64_t lmc0:1;
+               uint64_t l2c:1;
+               uint64_t reserved_15_15:1;
+               uint64_t rad:1;
+               uint64_t usb:1;
+               uint64_t pow:1;
+               uint64_t tim:1;
+               uint64_t pko:1;
+               uint64_t ipd:1;
+               uint64_t reserved_6_8:3;
+               uint64_t fpa:1;
+               uint64_t key:1;
+               uint64_t sli:1;
+               uint64_t reserved_2_2:1;
+               uint64_t gmx0:1;
+               uint64_t mio:1;
+#else
+               uint64_t mio:1;
+               uint64_t gmx0:1;
+               uint64_t reserved_2_2:1;
+               uint64_t sli:1;
+               uint64_t key:1;
+               uint64_t fpa:1;
+               uint64_t reserved_6_8:3;
+               uint64_t ipd:1;
+               uint64_t pko:1;
+               uint64_t tim:1;
+               uint64_t pow:1;
+               uint64_t usb:1;
+               uint64_t rad:1;
+               uint64_t reserved_15_15:1;
+               uint64_t l2c:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_18_19:2;
+               uint64_t pip:1;
+               uint64_t reserved_21_21:1;
+               uint64_t asxpcs0:1;
+               uint64_t reserved_23_24:2;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_27_29:3;
+               uint64_t iob:1;
+               uint64_t reserved_31_40:10;
+               uint64_t dpi:1;
+               uint64_t ptp:1;
+               uint64_t reserved_43_63:21;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_dint {
+       uint64_t u64;
+       struct cvmx_ciu_dint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t dint:32;
+#else
+               uint64_t dint:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu_dint_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t dint:1;
+#else
+               uint64_t dint:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } cn30xx;
+       struct cvmx_ciu_dint_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_2_63:62;
+               uint64_t dint:2;
+#else
+               uint64_t dint:2;
+               uint64_t reserved_2_63:62;
+#endif
+       } cn31xx;
+       struct cvmx_ciu_dint_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t dint:16;
+#else
+               uint64_t dint:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn38xx;
+       struct cvmx_ciu_dint_cn38xx cn38xxp2;
+       struct cvmx_ciu_dint_cn31xx cn50xx;
+       struct cvmx_ciu_dint_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t dint:4;
+#else
+               uint64_t dint:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_dint_cn52xx cn52xxp1;
+       struct cvmx_ciu_dint_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t dint:12;
+#else
+               uint64_t dint:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_dint_cn56xx cn56xxp1;
+       struct cvmx_ciu_dint_cn38xx cn58xx;
+       struct cvmx_ciu_dint_cn38xx cn58xxp1;
+       struct cvmx_ciu_dint_cn52xx cn61xx;
+       struct cvmx_ciu_dint_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_6_63:58;
+               uint64_t dint:6;
+#else
+               uint64_t dint:6;
+               uint64_t reserved_6_63:58;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_dint_cn63xx cn63xxp1;
+       struct cvmx_ciu_dint_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t dint:10;
+#else
+               uint64_t dint:10;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_dint_s cn68xx;
+       struct cvmx_ciu_dint_s cn68xxp1;
+       struct cvmx_ciu_dint_cn52xx cnf71xx;
+};
+
+union cvmx_ciu_en2_iox_int {
+       uint64_t u64;
+       struct cvmx_ciu_en2_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_iox_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_iox_int_cn61xx cn66xx;
+       struct cvmx_ciu_en2_iox_int_s cnf71xx;
+};
+
+union cvmx_ciu_en2_iox_int_w1c {
+       uint64_t u64;
+       struct cvmx_ciu_en2_iox_int_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_iox_int_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx;
+       struct cvmx_ciu_en2_iox_int_w1c_s cnf71xx;
+};
+
+union cvmx_ciu_en2_iox_int_w1s {
+       uint64_t u64;
+       struct cvmx_ciu_en2_iox_int_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_iox_int_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx;
+       struct cvmx_ciu_en2_iox_int_w1s_s cnf71xx;
+};
+
+union cvmx_ciu_en2_ppx_ip2 {
+       uint64_t u64;
+       struct cvmx_ciu_en2_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_ppx_ip2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_ppx_ip2_cn61xx cn66xx;
+       struct cvmx_ciu_en2_ppx_ip2_s cnf71xx;
+};
+
+union cvmx_ciu_en2_ppx_ip2_w1c {
+       uint64_t u64;
+       struct cvmx_ciu_en2_ppx_ip2_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx;
+       struct cvmx_ciu_en2_ppx_ip2_w1c_s cnf71xx;
+};
+
+union cvmx_ciu_en2_ppx_ip2_w1s {
+       uint64_t u64;
+       struct cvmx_ciu_en2_ppx_ip2_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx;
+       struct cvmx_ciu_en2_ppx_ip2_w1s_s cnf71xx;
+};
+
+union cvmx_ciu_en2_ppx_ip3 {
+       uint64_t u64;
+       struct cvmx_ciu_en2_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_ppx_ip3_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_ppx_ip3_cn61xx cn66xx;
+       struct cvmx_ciu_en2_ppx_ip3_s cnf71xx;
+};
+
+union cvmx_ciu_en2_ppx_ip3_w1c {
+       uint64_t u64;
+       struct cvmx_ciu_en2_ppx_ip3_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx;
+       struct cvmx_ciu_en2_ppx_ip3_w1c_s cnf71xx;
+};
+
+union cvmx_ciu_en2_ppx_ip3_w1s {
+       uint64_t u64;
+       struct cvmx_ciu_en2_ppx_ip3_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx;
+       struct cvmx_ciu_en2_ppx_ip3_w1s_s cnf71xx;
+};
+
+union cvmx_ciu_en2_ppx_ip4 {
+       uint64_t u64;
+       struct cvmx_ciu_en2_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_ppx_ip4_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_ppx_ip4_cn61xx cn66xx;
+       struct cvmx_ciu_en2_ppx_ip4_s cnf71xx;
+};
+
+union cvmx_ciu_en2_ppx_ip4_w1c {
+       uint64_t u64;
+       struct cvmx_ciu_en2_ppx_ip4_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx;
+       struct cvmx_ciu_en2_ppx_ip4_w1c_s cnf71xx;
+};
+
+union cvmx_ciu_en2_ppx_ip4_w1s {
+       uint64_t u64;
+       struct cvmx_ciu_en2_ppx_ip4_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
+       } s;
+       struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx;
+       struct cvmx_ciu_en2_ppx_ip4_w1s_s cnf71xx;
+};
+
+union cvmx_ciu_fuse {
+       uint64_t u64;
+       struct cvmx_ciu_fuse_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t fuse:32;
+#else
+               uint64_t fuse:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu_fuse_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t fuse:1;
+#else
+               uint64_t fuse:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } cn30xx;
+       struct cvmx_ciu_fuse_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_2_63:62;
+               uint64_t fuse:2;
+#else
+               uint64_t fuse:2;
+               uint64_t reserved_2_63:62;
+#endif
+       } cn31xx;
+       struct cvmx_ciu_fuse_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t fuse:16;
+#else
+               uint64_t fuse:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn38xx;
+       struct cvmx_ciu_fuse_cn38xx cn38xxp2;
+       struct cvmx_ciu_fuse_cn31xx cn50xx;
+       struct cvmx_ciu_fuse_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t fuse:4;
+#else
+               uint64_t fuse:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_fuse_cn52xx cn52xxp1;
+       struct cvmx_ciu_fuse_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t fuse:12;
+#else
+               uint64_t fuse:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_fuse_cn56xx cn56xxp1;
+       struct cvmx_ciu_fuse_cn38xx cn58xx;
+       struct cvmx_ciu_fuse_cn38xx cn58xxp1;
+       struct cvmx_ciu_fuse_cn52xx cn61xx;
+       struct cvmx_ciu_fuse_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_6_63:58;
+               uint64_t fuse:6;
+#else
+               uint64_t fuse:6;
+               uint64_t reserved_6_63:58;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_fuse_cn63xx cn63xxp1;
+       struct cvmx_ciu_fuse_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t fuse:10;
+#else
+               uint64_t fuse:10;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_fuse_s cn68xx;
+       struct cvmx_ciu_fuse_s cn68xxp1;
+       struct cvmx_ciu_fuse_cn52xx cnf71xx;
+};
+
+union cvmx_ciu_gstop {
+       uint64_t u64;
+       struct cvmx_ciu_gstop_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t gstop:1;
+#else
+               uint64_t gstop:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } s;
+       struct cvmx_ciu_gstop_s cn30xx;
+       struct cvmx_ciu_gstop_s cn31xx;
+       struct cvmx_ciu_gstop_s cn38xx;
+       struct cvmx_ciu_gstop_s cn38xxp2;
+       struct cvmx_ciu_gstop_s cn50xx;
+       struct cvmx_ciu_gstop_s cn52xx;
+       struct cvmx_ciu_gstop_s cn52xxp1;
+       struct cvmx_ciu_gstop_s cn56xx;
+       struct cvmx_ciu_gstop_s cn56xxp1;
+       struct cvmx_ciu_gstop_s cn58xx;
+       struct cvmx_ciu_gstop_s cn58xxp1;
+       struct cvmx_ciu_gstop_s cn61xx;
+       struct cvmx_ciu_gstop_s cn63xx;
+       struct cvmx_ciu_gstop_s cn63xxp1;
+       struct cvmx_ciu_gstop_s cn66xx;
+       struct cvmx_ciu_gstop_s cn68xx;
+       struct cvmx_ciu_gstop_s cn68xxp1;
+       struct cvmx_ciu_gstop_s cnf71xx;
+};
+
+union cvmx_ciu_intx_en0 {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_59_63:5;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_47_47:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t reserved_47_47:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t reserved_59_63:5;
+#endif
+       } cn30xx;
+       struct cvmx_ciu_intx_en0_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_59_63:5;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t reserved_59_63:5;
+#endif
+       } cn31xx;
+       struct cvmx_ciu_intx_en0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn38xx;
+       struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
+       struct cvmx_ciu_intx_en0_cn30xx cn50xx;
+       struct cvmx_ciu_intx_en0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
+       struct cvmx_ciu_intx_en0_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
+       struct cvmx_ciu_intx_en0_cn38xx cn58xx;
+       struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
+       struct cvmx_ciu_intx_en0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en0_cn52xx cn63xx;
+       struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
+       struct cvmx_ciu_intx_en0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t reserved_57_57:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_57:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en0_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t reserved_62_62:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t reserved_62_62:1;
+               uint64_t bootdma:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en0_w1c {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en0_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en0_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en0_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en0_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_en0_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
+       struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
+       struct cvmx_ciu_intx_en0_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t reserved_57_57:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_57:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en0_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t reserved_62_62:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t reserved_62_62:1;
+               uint64_t bootdma:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en0_w1s {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en0_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en0_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en0_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en0_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_en0_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
+       struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
+       struct cvmx_ciu_intx_en0_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t reserved_57_57:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_57:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en0_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t reserved_62_62:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t reserved_62_62:1;
+               uint64_t bootdma:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en1 {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en1_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t wdog:1;
+#else
+               uint64_t wdog:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } cn30xx;
+       struct cvmx_ciu_intx_en1_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_2_63:62;
+               uint64_t wdog:2;
+#else
+               uint64_t wdog:2;
+               uint64_t reserved_2_63:62;
+#endif
+       } cn31xx;
+       struct cvmx_ciu_intx_en1_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn38xx;
+       struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
+       struct cvmx_ciu_intx_en1_cn31xx cn50xx;
+       struct cvmx_ciu_intx_en1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_20_63:44;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t reserved_4_15:12;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_15:12;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t reserved_20_63:44;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_19_63:45;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t reserved_4_15:12;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_15:12;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t reserved_19_63:45;
+#endif
+       } cn52xxp1;
+       struct cvmx_ciu_intx_en1_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t wdog:12;
+#else
+               uint64_t wdog:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
+       struct cvmx_ciu_intx_en1_cn38xx cn58xx;
+       struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
+       struct cvmx_ciu_intx_en1_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_4_17:14;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en1_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_57_62:6;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_6_17:12;
+               uint64_t wdog:6;
+#else
+               uint64_t wdog:6;
+               uint64_t reserved_6_17:12;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_62:6;
+               uint64_t rst:1;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
+       struct cvmx_ciu_intx_en1_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en1_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t reserved_41_46:6;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t reserved_32_32:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_28_28:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_4_18:15;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_46:6;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en1_w1c {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en1_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en1_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_20_63:44;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t reserved_4_15:12;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_15:12;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t reserved_20_63:44;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en1_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t wdog:12;
+#else
+               uint64_t wdog:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en1_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_en1_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_4_17:14;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en1_w1c_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_57_62:6;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_6_17:12;
+               uint64_t wdog:6;
+#else
+               uint64_t wdog:6;
+               uint64_t reserved_6_17:12;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_62:6;
+               uint64_t rst:1;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
+       struct cvmx_ciu_intx_en1_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en1_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t reserved_41_46:6;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t reserved_32_32:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_28_28:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_4_18:15;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_46:6;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en1_w1s {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en1_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en1_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_20_63:44;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t reserved_4_15:12;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_15:12;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t reserved_20_63:44;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en1_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t wdog:12;
+#else
+               uint64_t wdog:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en1_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_en1_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_4_17:14;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en1_w1s_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_57_62:6;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_6_17:12;
+               uint64_t wdog:6;
+#else
+               uint64_t wdog:6;
+               uint64_t reserved_6_17:12;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_62:6;
+               uint64_t rst:1;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
+       struct cvmx_ciu_intx_en1_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en1_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t reserved_41_46:6;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t reserved_32_32:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_28_28:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_4_18:15;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_46:6;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en4_0 {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en4_0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en4_0_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_59_63:5;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_47_47:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t reserved_47_47:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t reserved_59_63:5;
+#endif
+       } cn50xx;
+       struct cvmx_ciu_intx_en4_0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
+       struct cvmx_ciu_intx_en4_0_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
+       struct cvmx_ciu_intx_en4_0_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
+       struct cvmx_ciu_intx_en4_0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
+       struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
+       struct cvmx_ciu_intx_en4_0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t reserved_57_57:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_57:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en4_0_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t reserved_62_62:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t reserved_62_62:1;
+               uint64_t bootdma:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en4_0_w1c {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en4_0_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en4_0_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_en4_0_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
+       struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
+       struct cvmx_ciu_intx_en4_0_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t reserved_57_57:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_57:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en4_0_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t reserved_62_62:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t reserved_62_62:1;
+               uint64_t bootdma:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en4_0_w1s {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en4_0_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en4_0_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_en4_0_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
+       struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
+       struct cvmx_ciu_intx_en4_0_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t reserved_57_57:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_57:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en4_0_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t reserved_62_62:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t reserved_44_44:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t reserved_44_44:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t reserved_62_62:1;
+               uint64_t bootdma:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en4_1 {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en4_1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en4_1_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_2_63:62;
+               uint64_t wdog:2;
+#else
+               uint64_t wdog:2;
+               uint64_t reserved_2_63:62;
+#endif
+       } cn50xx;
+       struct cvmx_ciu_intx_en4_1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_20_63:44;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t reserved_4_15:12;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_15:12;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t reserved_20_63:44;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en4_1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_19_63:45;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t reserved_4_15:12;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_15:12;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t reserved_19_63:45;
+#endif
+       } cn52xxp1;
+       struct cvmx_ciu_intx_en4_1_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t wdog:12;
+#else
+               uint64_t wdog:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
+       struct cvmx_ciu_intx_en4_1_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
+       struct cvmx_ciu_intx_en4_1_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_4_17:14;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en4_1_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_57_62:6;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_6_17:12;
+               uint64_t wdog:6;
+#else
+               uint64_t wdog:6;
+               uint64_t reserved_6_17:12;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_62:6;
+               uint64_t rst:1;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
+       struct cvmx_ciu_intx_en4_1_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en4_1_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t reserved_41_46:6;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t reserved_32_32:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_28_28:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_4_18:15;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_46:6;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en4_1_w1c {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en4_1_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_20_63:44;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t reserved_4_15:12;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_15:12;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t reserved_20_63:44;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t wdog:12;
+#else
+               uint64_t wdog:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_en4_1_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_4_17:14;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_57_62:6;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_6_17:12;
+               uint64_t wdog:6;
+#else
+               uint64_t wdog:6;
+               uint64_t reserved_6_17:12;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_62:6;
+               uint64_t rst:1;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
+       struct cvmx_ciu_intx_en4_1_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en4_1_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t reserved_41_46:6;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t reserved_32_32:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_28_28:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_4_18:15;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_46:6;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_en4_1_w1s {
+       uint64_t u64;
+       struct cvmx_ciu_intx_en4_1_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_20_63:44;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t reserved_4_15:12;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_15:12;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t reserved_20_63:44;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t wdog:12;
+#else
+               uint64_t wdog:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_en4_1_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_4_17:14;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_57_62:6;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_6_17:12;
+               uint64_t wdog:6;
+#else
+               uint64_t wdog:6;
+               uint64_t reserved_6_17:12;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_62:6;
+               uint64_t rst:1;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
+       struct cvmx_ciu_intx_en4_1_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_en4_1_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t reserved_41_46:6;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t reserved_32_32:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_28_28:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_4_18:15;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_46:6;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_sum0 {
+       uint64_t u64;
+       struct cvmx_ciu_intx_sum0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_sum0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_59_63:5;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_47_47:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t reserved_47_47:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t reserved_59_63:5;
+#endif
+       } cn30xx;
+       struct cvmx_ciu_intx_sum0_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_59_63:5;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t reserved_59_63:5;
+#endif
+       } cn31xx;
+       struct cvmx_ciu_intx_sum0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn38xx;
+       struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
+       struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
+       struct cvmx_ciu_intx_sum0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
+       struct cvmx_ciu_intx_sum0_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
+       struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
+       struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
+       struct cvmx_ciu_intx_sum0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t sum2:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t sum2:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
+       struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
+       struct cvmx_ciu_intx_sum0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t reserved_57_57:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t sum2:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t sum2:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_57:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_sum0_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t reserved_62_62:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t sum2:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t sum2:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t reserved_62_62:1;
+               uint64_t bootdma:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_intx_sum4 {
+       uint64_t u64;
+       struct cvmx_ciu_intx_sum4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } s;
+       struct cvmx_ciu_intx_sum4_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_59_63:5;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_47_47:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t reserved_47_47:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t reserved_59_63:5;
+#endif
+       } cn50xx;
+       struct cvmx_ciu_intx_sum4_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
+       struct cvmx_ciu_intx_sum4_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
+       struct cvmx_ciu_intx_sum4_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t timer:4;
+               uint64_t key_zero:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t key_zero:1;
+               uint64_t timer:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn58xx;
+       struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
+       struct cvmx_ciu_intx_sum4_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t sum2:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t sum2:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_intx_sum4_cn52xx cn63xx;
+       struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1;
+       struct cvmx_ciu_intx_sum4_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t reserved_57_57:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t sum2:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t sum2:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_57:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_intx_sum4_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t reserved_62_62:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t sum2:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t sum2:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t reserved_62_62:1;
+               uint64_t bootdma:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_int33_sum0 {
+       uint64_t u64;
+       struct cvmx_ciu_int33_sum0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t sum2:1;
+               uint64_t ipd_drp:1;
+               uint64_t gmx_drp:2;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t sum2:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } s;
+       struct cvmx_ciu_int33_sum0_s cn61xx;
+       struct cvmx_ciu_int33_sum0_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t reserved_57_58:2;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t reserved_51_51:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_51_51:1;
                uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn31xx;
-       struct cvmx_ciu_intx_en0_cn38xx {
-               uint64_t reserved_56_63:8;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
+               uint64_t usb:1;
+               uint64_t reserved_57_58:2;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_int33_sum0_cn63xx cn63xxp1;
+       struct cvmx_ciu_int33_sum0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t mii:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t reserved_57_57:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t sum2:1;
                uint64_t ipd_drp:1;
                uint64_t gmx_drp:2;
                uint64_t trace:1;
                uint64_t rml:1;
                uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
+               uint64_t wdog_sum:1;
+               uint64_t pci_msi:4;
+               uint64_t pci_int:4;
+               uint64_t uart:2;
+               uint64_t mbox:2;
+               uint64_t gpio:16;
+               uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:2;
+               uint64_t ipd_drp:1;
+               uint64_t sum2:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t reserved_57_57:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t mii:1;
+               uint64_t bootdma:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_int33_sum0_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t bootdma:1;
+               uint64_t reserved_62_62:1;
+               uint64_t ipdppthr:1;
+               uint64_t powiq:1;
+               uint64_t twsi2:1;
+               uint64_t mpi:1;
+               uint64_t pcm:1;
+               uint64_t usb:1;
+               uint64_t timer:4;
+               uint64_t sum2:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t gmx_drp:1;
+               uint64_t trace:1;
+               uint64_t rml:1;
+               uint64_t twsi:1;
+               uint64_t wdog_sum:1;
                uint64_t pci_msi:4;
                uint64_t pci_int:4;
                uint64_t uart:2;
                uint64_t mbox:2;
                uint64_t gpio:16;
                uint64_t workq:16;
+#else
+               uint64_t workq:16;
+               uint64_t gpio:16;
+               uint64_t mbox:2;
+               uint64_t uart:2;
+               uint64_t pci_int:4;
+               uint64_t pci_msi:4;
+               uint64_t wdog_sum:1;
+               uint64_t twsi:1;
+               uint64_t rml:1;
+               uint64_t trace:1;
+               uint64_t gmx_drp:1;
+               uint64_t reserved_49_49:1;
+               uint64_t ipd_drp:1;
+               uint64_t sum2:1;
+               uint64_t timer:4;
+               uint64_t usb:1;
+               uint64_t pcm:1;
+               uint64_t mpi:1;
+               uint64_t twsi2:1;
+               uint64_t powiq:1;
+               uint64_t ipdppthr:1;
+               uint64_t reserved_62_62:1;
+               uint64_t bootdma:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_int_dbg_sel {
+       uint64_t u64;
+       struct cvmx_ciu_int_dbg_sel_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_19_63:45;
+               uint64_t sel:3;
+               uint64_t reserved_10_15:6;
+               uint64_t irq:2;
+               uint64_t reserved_5_7:3;
+               uint64_t pp:5;
+#else
+               uint64_t pp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t irq:2;
+               uint64_t reserved_10_15:6;
+               uint64_t sel:3;
+               uint64_t reserved_19_63:45;
+#endif
+       } s;
+       struct cvmx_ciu_int_dbg_sel_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_19_63:45;
+               uint64_t sel:3;
+               uint64_t reserved_10_15:6;
+               uint64_t irq:2;
+               uint64_t reserved_4_7:4;
+               uint64_t pp:4;
+#else
+               uint64_t pp:4;
+               uint64_t reserved_4_7:4;
+               uint64_t irq:2;
+               uint64_t reserved_10_15:6;
+               uint64_t sel:3;
+               uint64_t reserved_19_63:45;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_int_dbg_sel_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_19_63:45;
+               uint64_t sel:3;
+               uint64_t reserved_10_15:6;
+               uint64_t irq:2;
+               uint64_t reserved_3_7:5;
+               uint64_t pp:3;
+#else
+               uint64_t pp:3;
+               uint64_t reserved_3_7:5;
+               uint64_t irq:2;
+               uint64_t reserved_10_15:6;
+               uint64_t sel:3;
+               uint64_t reserved_19_63:45;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_int_dbg_sel_cn61xx cn66xx;
+       struct cvmx_ciu_int_dbg_sel_s cn68xx;
+       struct cvmx_ciu_int_dbg_sel_s cn68xxp1;
+       struct cvmx_ciu_int_dbg_sel_cn61xx cnf71xx;
+};
+
+union cvmx_ciu_int_sum1 {
+       uint64_t u64;
+       struct cvmx_ciu_int_sum1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu_int_sum1_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t wdog:1;
+#else
+               uint64_t wdog:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } cn30xx;
+       struct cvmx_ciu_int_sum1_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_2_63:62;
+               uint64_t wdog:2;
+#else
+               uint64_t wdog:2;
+               uint64_t reserved_2_63:62;
+#endif
+       } cn31xx;
+       struct cvmx_ciu_int_sum1_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t wdog:16;
+#else
+               uint64_t wdog:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn38xx;
+       struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
+       struct cvmx_ciu_int_sum1_cn31xx cn50xx;
+       struct cvmx_ciu_int_sum1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_20_63:44;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t reserved_4_15:12;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_15:12;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t reserved_20_63:44;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_int_sum1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_19_63:45;
+               uint64_t mii1:1;
+               uint64_t usb1:1;
+               uint64_t uart2:1;
+               uint64_t reserved_4_15:12;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_15:12;
+               uint64_t uart2:1;
+               uint64_t usb1:1;
+               uint64_t mii1:1;
+               uint64_t reserved_19_63:45;
+#endif
+       } cn52xxp1;
+       struct cvmx_ciu_int_sum1_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t wdog:12;
+#else
+               uint64_t wdog:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
+       struct cvmx_ciu_int_sum1_cn38xx cn58xx;
+       struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
+       struct cvmx_ciu_int_sum1_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_4_17:14;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_int_sum1_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_57_62:6;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t srio1:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_6_17:12;
+               uint64_t wdog:6;
+#else
+               uint64_t wdog:6;
+               uint64_t reserved_6_17:12;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_45:9;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t srio1:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_62:6;
+               uint64_t rst:1;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_int_sum1_cn63xx cn63xxp1;
+       struct cvmx_ciu_int_sum1_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_int_sum1_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t reserved_37_46:10;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t reserved_32_32:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_28_28:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_4_18:15;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_46:10;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_mbox_clrx {
+       uint64_t u64;
+       struct cvmx_ciu_mbox_clrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t bits:32;
+#else
+               uint64_t bits:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu_mbox_clrx_s cn30xx;
+       struct cvmx_ciu_mbox_clrx_s cn31xx;
+       struct cvmx_ciu_mbox_clrx_s cn38xx;
+       struct cvmx_ciu_mbox_clrx_s cn38xxp2;
+       struct cvmx_ciu_mbox_clrx_s cn50xx;
+       struct cvmx_ciu_mbox_clrx_s cn52xx;
+       struct cvmx_ciu_mbox_clrx_s cn52xxp1;
+       struct cvmx_ciu_mbox_clrx_s cn56xx;
+       struct cvmx_ciu_mbox_clrx_s cn56xxp1;
+       struct cvmx_ciu_mbox_clrx_s cn58xx;
+       struct cvmx_ciu_mbox_clrx_s cn58xxp1;
+       struct cvmx_ciu_mbox_clrx_s cn61xx;
+       struct cvmx_ciu_mbox_clrx_s cn63xx;
+       struct cvmx_ciu_mbox_clrx_s cn63xxp1;
+       struct cvmx_ciu_mbox_clrx_s cn66xx;
+       struct cvmx_ciu_mbox_clrx_s cn68xx;
+       struct cvmx_ciu_mbox_clrx_s cn68xxp1;
+       struct cvmx_ciu_mbox_clrx_s cnf71xx;
+};
+
+union cvmx_ciu_mbox_setx {
+       uint64_t u64;
+       struct cvmx_ciu_mbox_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t bits:32;
+#else
+               uint64_t bits:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu_mbox_setx_s cn30xx;
+       struct cvmx_ciu_mbox_setx_s cn31xx;
+       struct cvmx_ciu_mbox_setx_s cn38xx;
+       struct cvmx_ciu_mbox_setx_s cn38xxp2;
+       struct cvmx_ciu_mbox_setx_s cn50xx;
+       struct cvmx_ciu_mbox_setx_s cn52xx;
+       struct cvmx_ciu_mbox_setx_s cn52xxp1;
+       struct cvmx_ciu_mbox_setx_s cn56xx;
+       struct cvmx_ciu_mbox_setx_s cn56xxp1;
+       struct cvmx_ciu_mbox_setx_s cn58xx;
+       struct cvmx_ciu_mbox_setx_s cn58xxp1;
+       struct cvmx_ciu_mbox_setx_s cn61xx;
+       struct cvmx_ciu_mbox_setx_s cn63xx;
+       struct cvmx_ciu_mbox_setx_s cn63xxp1;
+       struct cvmx_ciu_mbox_setx_s cn66xx;
+       struct cvmx_ciu_mbox_setx_s cn68xx;
+       struct cvmx_ciu_mbox_setx_s cn68xxp1;
+       struct cvmx_ciu_mbox_setx_s cnf71xx;
+};
+
+union cvmx_ciu_nmi {
+       uint64_t u64;
+       struct cvmx_ciu_nmi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t nmi:32;
+#else
+               uint64_t nmi:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu_nmi_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t nmi:1;
+#else
+               uint64_t nmi:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } cn30xx;
+       struct cvmx_ciu_nmi_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_2_63:62;
+               uint64_t nmi:2;
+#else
+               uint64_t nmi:2;
+               uint64_t reserved_2_63:62;
+#endif
+       } cn31xx;
+       struct cvmx_ciu_nmi_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t nmi:16;
+#else
+               uint64_t nmi:16;
+               uint64_t reserved_16_63:48;
+#endif
        } cn38xx;
-       struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
-       struct cvmx_ciu_intx_en0_cn30xx cn50xx;
-       struct cvmx_ciu_intx_en0_cn52xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
+       struct cvmx_ciu_nmi_cn38xx cn38xxp2;
+       struct cvmx_ciu_nmi_cn31xx cn50xx;
+       struct cvmx_ciu_nmi_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t nmi:4;
+#else
+               uint64_t nmi:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_nmi_cn52xx cn52xxp1;
+       struct cvmx_ciu_nmi_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t nmi:12;
+#else
+               uint64_t nmi:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_nmi_cn56xx cn56xxp1;
+       struct cvmx_ciu_nmi_cn38xx cn58xx;
+       struct cvmx_ciu_nmi_cn38xx cn58xxp1;
+       struct cvmx_ciu_nmi_cn52xx cn61xx;
+       struct cvmx_ciu_nmi_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_6_63:58;
+               uint64_t nmi:6;
+#else
+               uint64_t nmi:6;
+               uint64_t reserved_6_63:58;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_nmi_cn63xx cn63xxp1;
+       struct cvmx_ciu_nmi_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t nmi:10;
+#else
+               uint64_t nmi:10;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_nmi_s cn68xx;
+       struct cvmx_ciu_nmi_s cn68xxp1;
+       struct cvmx_ciu_nmi_cn52xx cnf71xx;
+};
+
+union cvmx_ciu_pci_inta {
+       uint64_t u64;
+       struct cvmx_ciu_pci_inta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_2_63:62;
+               uint64_t intr:2;
+#else
+               uint64_t intr:2;
+               uint64_t reserved_2_63:62;
+#endif
+       } s;
+       struct cvmx_ciu_pci_inta_s cn30xx;
+       struct cvmx_ciu_pci_inta_s cn31xx;
+       struct cvmx_ciu_pci_inta_s cn38xx;
+       struct cvmx_ciu_pci_inta_s cn38xxp2;
+       struct cvmx_ciu_pci_inta_s cn50xx;
+       struct cvmx_ciu_pci_inta_s cn52xx;
+       struct cvmx_ciu_pci_inta_s cn52xxp1;
+       struct cvmx_ciu_pci_inta_s cn56xx;
+       struct cvmx_ciu_pci_inta_s cn56xxp1;
+       struct cvmx_ciu_pci_inta_s cn58xx;
+       struct cvmx_ciu_pci_inta_s cn58xxp1;
+       struct cvmx_ciu_pci_inta_s cn61xx;
+       struct cvmx_ciu_pci_inta_s cn63xx;
+       struct cvmx_ciu_pci_inta_s cn63xxp1;
+       struct cvmx_ciu_pci_inta_s cn66xx;
+       struct cvmx_ciu_pci_inta_s cn68xx;
+       struct cvmx_ciu_pci_inta_s cn68xxp1;
+       struct cvmx_ciu_pci_inta_s cnf71xx;
+};
+
+union cvmx_ciu_pp_bist_stat {
+       uint64_t u64;
+       struct cvmx_ciu_pp_bist_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t pp_bist:32;
+#else
+               uint64_t pp_bist:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu_pp_bist_stat_s cn68xx;
+       struct cvmx_ciu_pp_bist_stat_s cn68xxp1;
+};
+
+union cvmx_ciu_pp_dbg {
+       uint64_t u64;
+       struct cvmx_ciu_pp_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t ppdbg:32;
+#else
+               uint64_t ppdbg:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu_pp_dbg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t ppdbg:1;
+#else
+               uint64_t ppdbg:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } cn30xx;
+       struct cvmx_ciu_pp_dbg_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_2_63:62;
+               uint64_t ppdbg:2;
+#else
+               uint64_t ppdbg:2;
+               uint64_t reserved_2_63:62;
+#endif
+       } cn31xx;
+       struct cvmx_ciu_pp_dbg_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t ppdbg:16;
+#else
+               uint64_t ppdbg:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn38xx;
+       struct cvmx_ciu_pp_dbg_cn38xx cn38xxp2;
+       struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
+       struct cvmx_ciu_pp_dbg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t ppdbg:4;
+#else
+               uint64_t ppdbg:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
+       struct cvmx_ciu_pp_dbg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t ppdbg:12;
+#else
+               uint64_t ppdbg:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn56xx;
+       struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
+       struct cvmx_ciu_pp_dbg_cn38xx cn58xx;
+       struct cvmx_ciu_pp_dbg_cn38xx cn58xxp1;
+       struct cvmx_ciu_pp_dbg_cn52xx cn61xx;
+       struct cvmx_ciu_pp_dbg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_6_63:58;
+               uint64_t ppdbg:6;
+#else
+               uint64_t ppdbg:6;
+               uint64_t reserved_6_63:58;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1;
+       struct cvmx_ciu_pp_dbg_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t ppdbg:10;
+#else
+               uint64_t ppdbg:10;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_pp_dbg_s cn68xx;
+       struct cvmx_ciu_pp_dbg_s cn68xxp1;
+       struct cvmx_ciu_pp_dbg_cn52xx cnf71xx;
+};
+
+union cvmx_ciu_pp_pokex {
+       uint64_t u64;
+       struct cvmx_ciu_pp_pokex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t poke:64;
+#else
+               uint64_t poke:64;
+#endif
+       } s;
+       struct cvmx_ciu_pp_pokex_s cn30xx;
+       struct cvmx_ciu_pp_pokex_s cn31xx;
+       struct cvmx_ciu_pp_pokex_s cn38xx;
+       struct cvmx_ciu_pp_pokex_s cn38xxp2;
+       struct cvmx_ciu_pp_pokex_s cn50xx;
+       struct cvmx_ciu_pp_pokex_s cn52xx;
+       struct cvmx_ciu_pp_pokex_s cn52xxp1;
+       struct cvmx_ciu_pp_pokex_s cn56xx;
+       struct cvmx_ciu_pp_pokex_s cn56xxp1;
+       struct cvmx_ciu_pp_pokex_s cn58xx;
+       struct cvmx_ciu_pp_pokex_s cn58xxp1;
+       struct cvmx_ciu_pp_pokex_s cn61xx;
+       struct cvmx_ciu_pp_pokex_s cn63xx;
+       struct cvmx_ciu_pp_pokex_s cn63xxp1;
+       struct cvmx_ciu_pp_pokex_s cn66xx;
+       struct cvmx_ciu_pp_pokex_s cn68xx;
+       struct cvmx_ciu_pp_pokex_s cn68xxp1;
+       struct cvmx_ciu_pp_pokex_s cnf71xx;
+};
+
+union cvmx_ciu_pp_rst {
+       uint64_t u64;
+       struct cvmx_ciu_pp_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t rst:31;
+               uint64_t rst0:1;
+#else
+               uint64_t rst0:1;
+               uint64_t rst:31;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu_pp_rst_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t rst0:1;
+#else
+               uint64_t rst0:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } cn30xx;
+       struct cvmx_ciu_pp_rst_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_2_63:62;
+               uint64_t rst:1;
+               uint64_t rst0:1;
+#else
+               uint64_t rst0:1;
+               uint64_t rst:1;
+               uint64_t reserved_2_63:62;
+#endif
+       } cn31xx;
+       struct cvmx_ciu_pp_rst_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t rst:15;
+               uint64_t rst0:1;
+#else
+               uint64_t rst0:1;
+               uint64_t rst:15;
+               uint64_t reserved_16_63:48;
+#endif
+       } cn38xx;
+       struct cvmx_ciu_pp_rst_cn38xx cn38xxp2;
+       struct cvmx_ciu_pp_rst_cn31xx cn50xx;
+       struct cvmx_ciu_pp_rst_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t rst:3;
+               uint64_t rst0:1;
+#else
+               uint64_t rst0:1;
+               uint64_t rst:3;
+               uint64_t reserved_4_63:60;
+#endif
        } cn52xx;
-       struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
-       struct cvmx_ciu_intx_en0_cn56xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
+       struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
+       struct cvmx_ciu_pp_rst_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t rst:11;
+               uint64_t rst0:1;
+#else
+               uint64_t rst0:1;
+               uint64_t rst:11;
+               uint64_t reserved_12_63:52;
+#endif
        } cn56xx;
-       struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
-       struct cvmx_ciu_intx_en0_cn38xx cn58xx;
-       struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
-       struct cvmx_ciu_intx_en0_cn52xx cn63xx;
-       struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
+       struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
+       struct cvmx_ciu_pp_rst_cn38xx cn58xx;
+       struct cvmx_ciu_pp_rst_cn38xx cn58xxp1;
+       struct cvmx_ciu_pp_rst_cn52xx cn61xx;
+       struct cvmx_ciu_pp_rst_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_6_63:58;
+               uint64_t rst:5;
+               uint64_t rst0:1;
+#else
+               uint64_t rst0:1;
+               uint64_t rst:5;
+               uint64_t reserved_6_63:58;
+#endif
+       } cn63xx;
+       struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
+       struct cvmx_ciu_pp_rst_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t rst:9;
+               uint64_t rst0:1;
+#else
+               uint64_t rst0:1;
+               uint64_t rst:9;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_pp_rst_s cn68xx;
+       struct cvmx_ciu_pp_rst_s cn68xxp1;
+       struct cvmx_ciu_pp_rst_cn52xx cnf71xx;
+};
+
+union cvmx_ciu_qlm0 {
+       uint64_t u64;
+       struct cvmx_ciu_qlm0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t g2bypass:1;
+               uint64_t reserved_53_62:10;
+               uint64_t g2deemph:5;
+               uint64_t reserved_45_47:3;
+               uint64_t g2margin:5;
+               uint64_t reserved_32_39:8;
+               uint64_t txbypass:1;
+               uint64_t reserved_21_30:10;
+               uint64_t txdeemph:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txmargin:5;
+               uint64_t reserved_4_7:4;
+               uint64_t lane_en:4;
+#else
+               uint64_t lane_en:4;
+               uint64_t reserved_4_7:4;
+               uint64_t txmargin:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txdeemph:5;
+               uint64_t reserved_21_30:10;
+               uint64_t txbypass:1;
+               uint64_t reserved_32_39:8;
+               uint64_t g2margin:5;
+               uint64_t reserved_45_47:3;
+               uint64_t g2deemph:5;
+               uint64_t reserved_53_62:10;
+               uint64_t g2bypass:1;
+#endif
+       } s;
+       struct cvmx_ciu_qlm0_s cn61xx;
+       struct cvmx_ciu_qlm0_s cn63xx;
+       struct cvmx_ciu_qlm0_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t txbypass:1;
+               uint64_t reserved_20_30:11;
+               uint64_t txdeemph:4;
+               uint64_t reserved_13_15:3;
+               uint64_t txmargin:5;
+               uint64_t reserved_4_7:4;
+               uint64_t lane_en:4;
+#else
+               uint64_t lane_en:4;
+               uint64_t reserved_4_7:4;
+               uint64_t txmargin:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txdeemph:4;
+               uint64_t reserved_20_30:11;
+               uint64_t txbypass:1;
+               uint64_t reserved_32_63:32;
+#endif
+       } cn63xxp1;
+       struct cvmx_ciu_qlm0_s cn66xx;
+       struct cvmx_ciu_qlm0_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t txbypass:1;
+               uint64_t reserved_21_30:10;
+               uint64_t txdeemph:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txmargin:5;
+               uint64_t reserved_4_7:4;
+               uint64_t lane_en:4;
+#else
+               uint64_t lane_en:4;
+               uint64_t reserved_4_7:4;
+               uint64_t txmargin:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txdeemph:5;
+               uint64_t reserved_21_30:10;
+               uint64_t txbypass:1;
+               uint64_t reserved_32_63:32;
+#endif
+       } cn68xx;
+       struct cvmx_ciu_qlm0_cn68xx cn68xxp1;
+       struct cvmx_ciu_qlm0_s cnf71xx;
+};
+
+union cvmx_ciu_qlm1 {
+       uint64_t u64;
+       struct cvmx_ciu_qlm1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t g2bypass:1;
+               uint64_t reserved_53_62:10;
+               uint64_t g2deemph:5;
+               uint64_t reserved_45_47:3;
+               uint64_t g2margin:5;
+               uint64_t reserved_32_39:8;
+               uint64_t txbypass:1;
+               uint64_t reserved_21_30:10;
+               uint64_t txdeemph:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txmargin:5;
+               uint64_t reserved_4_7:4;
+               uint64_t lane_en:4;
+#else
+               uint64_t lane_en:4;
+               uint64_t reserved_4_7:4;
+               uint64_t txmargin:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txdeemph:5;
+               uint64_t reserved_21_30:10;
+               uint64_t txbypass:1;
+               uint64_t reserved_32_39:8;
+               uint64_t g2margin:5;
+               uint64_t reserved_45_47:3;
+               uint64_t g2deemph:5;
+               uint64_t reserved_53_62:10;
+               uint64_t g2bypass:1;
+#endif
+       } s;
+       struct cvmx_ciu_qlm1_s cn61xx;
+       struct cvmx_ciu_qlm1_s cn63xx;
+       struct cvmx_ciu_qlm1_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t txbypass:1;
+               uint64_t reserved_20_30:11;
+               uint64_t txdeemph:4;
+               uint64_t reserved_13_15:3;
+               uint64_t txmargin:5;
+               uint64_t reserved_4_7:4;
+               uint64_t lane_en:4;
+#else
+               uint64_t lane_en:4;
+               uint64_t reserved_4_7:4;
+               uint64_t txmargin:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txdeemph:4;
+               uint64_t reserved_20_30:11;
+               uint64_t txbypass:1;
+               uint64_t reserved_32_63:32;
+#endif
+       } cn63xxp1;
+       struct cvmx_ciu_qlm1_s cn66xx;
+       struct cvmx_ciu_qlm1_s cn68xx;
+       struct cvmx_ciu_qlm1_s cn68xxp1;
+       struct cvmx_ciu_qlm1_s cnf71xx;
+};
+
+union cvmx_ciu_qlm2 {
+       uint64_t u64;
+       struct cvmx_ciu_qlm2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t g2bypass:1;
+               uint64_t reserved_53_62:10;
+               uint64_t g2deemph:5;
+               uint64_t reserved_45_47:3;
+               uint64_t g2margin:5;
+               uint64_t reserved_32_39:8;
+               uint64_t txbypass:1;
+               uint64_t reserved_21_30:10;
+               uint64_t txdeemph:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txmargin:5;
+               uint64_t reserved_4_7:4;
+               uint64_t lane_en:4;
+#else
+               uint64_t lane_en:4;
+               uint64_t reserved_4_7:4;
+               uint64_t txmargin:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txdeemph:5;
+               uint64_t reserved_21_30:10;
+               uint64_t txbypass:1;
+               uint64_t reserved_32_39:8;
+               uint64_t g2margin:5;
+               uint64_t reserved_45_47:3;
+               uint64_t g2deemph:5;
+               uint64_t reserved_53_62:10;
+               uint64_t g2bypass:1;
+#endif
+       } s;
+       struct cvmx_ciu_qlm2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t txbypass:1;
+               uint64_t reserved_21_30:10;
+               uint64_t txdeemph:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txmargin:5;
+               uint64_t reserved_4_7:4;
+               uint64_t lane_en:4;
+#else
+               uint64_t lane_en:4;
+               uint64_t reserved_4_7:4;
+               uint64_t txmargin:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txdeemph:5;
+               uint64_t reserved_21_30:10;
+               uint64_t txbypass:1;
+               uint64_t reserved_32_63:32;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_qlm2_cn61xx cn63xx;
+       struct cvmx_ciu_qlm2_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t txbypass:1;
+               uint64_t reserved_20_30:11;
+               uint64_t txdeemph:4;
+               uint64_t reserved_13_15:3;
+               uint64_t txmargin:5;
+               uint64_t reserved_4_7:4;
+               uint64_t lane_en:4;
+#else
+               uint64_t lane_en:4;
+               uint64_t reserved_4_7:4;
+               uint64_t txmargin:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txdeemph:4;
+               uint64_t reserved_20_30:11;
+               uint64_t txbypass:1;
+               uint64_t reserved_32_63:32;
+#endif
+       } cn63xxp1;
+       struct cvmx_ciu_qlm2_cn61xx cn66xx;
+       struct cvmx_ciu_qlm2_s cn68xx;
+       struct cvmx_ciu_qlm2_s cn68xxp1;
+       struct cvmx_ciu_qlm2_cn61xx cnf71xx;
 };
 
-union cvmx_ciu_intx_en0_w1c {
+union cvmx_ciu_qlm3 {
        uint64_t u64;
-       struct cvmx_ciu_intx_en0_w1c_s {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
+       struct cvmx_ciu_qlm3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t g2bypass:1;
+               uint64_t reserved_53_62:10;
+               uint64_t g2deemph:5;
+               uint64_t reserved_45_47:3;
+               uint64_t g2margin:5;
+               uint64_t reserved_32_39:8;
+               uint64_t txbypass:1;
+               uint64_t reserved_21_30:10;
+               uint64_t txdeemph:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txmargin:5;
+               uint64_t reserved_4_7:4;
+               uint64_t lane_en:4;
+#else
+               uint64_t lane_en:4;
+               uint64_t reserved_4_7:4;
+               uint64_t txmargin:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txdeemph:5;
+               uint64_t reserved_21_30:10;
+               uint64_t txbypass:1;
+               uint64_t reserved_32_39:8;
+               uint64_t g2margin:5;
+               uint64_t reserved_45_47:3;
+               uint64_t g2deemph:5;
+               uint64_t reserved_53_62:10;
+               uint64_t g2bypass:1;
+#endif
        } s;
-       struct cvmx_ciu_intx_en0_w1c_cn52xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn52xx;
-       struct cvmx_ciu_intx_en0_w1c_s cn56xx;
-       struct cvmx_ciu_intx_en0_w1c_cn58xx {
-               uint64_t reserved_56_63:8;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
-       struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
+       struct cvmx_ciu_qlm3_s cn68xx;
+       struct cvmx_ciu_qlm3_s cn68xxp1;
 };
 
-union cvmx_ciu_intx_en0_w1s {
+union cvmx_ciu_qlm4 {
        uint64_t u64;
-       struct cvmx_ciu_intx_en0_w1s_s {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
+       struct cvmx_ciu_qlm4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t g2bypass:1;
+               uint64_t reserved_53_62:10;
+               uint64_t g2deemph:5;
+               uint64_t reserved_45_47:3;
+               uint64_t g2margin:5;
+               uint64_t reserved_32_39:8;
+               uint64_t txbypass:1;
+               uint64_t reserved_21_30:10;
+               uint64_t txdeemph:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txmargin:5;
+               uint64_t reserved_4_7:4;
+               uint64_t lane_en:4;
+#else
+               uint64_t lane_en:4;
+               uint64_t reserved_4_7:4;
+               uint64_t txmargin:5;
+               uint64_t reserved_13_15:3;
+               uint64_t txdeemph:5;
+               uint64_t reserved_21_30:10;
+               uint64_t txbypass:1;
+               uint64_t reserved_32_39:8;
+               uint64_t g2margin:5;
+               uint64_t reserved_45_47:3;
+               uint64_t g2deemph:5;
+               uint64_t reserved_53_62:10;
+               uint64_t g2bypass:1;
+#endif
        } s;
-       struct cvmx_ciu_intx_en0_w1s_cn52xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn52xx;
-       struct cvmx_ciu_intx_en0_w1s_s cn56xx;
-       struct cvmx_ciu_intx_en0_w1s_cn58xx {
-               uint64_t reserved_56_63:8;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
-       struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
+       struct cvmx_ciu_qlm4_s cn68xx;
+       struct cvmx_ciu_qlm4_s cn68xxp1;
 };
 
-union cvmx_ciu_intx_en1 {
+union cvmx_ciu_qlm_dcok {
        uint64_t u64;
-       struct cvmx_ciu_intx_en1_s {
-               uint64_t rst:1;
-               uint64_t reserved_57_62:6;
-               uint64_t dfm:1;
-               uint64_t reserved_53_55:3;
-               uint64_t lmc0:1;
-               uint64_t srio1:1;
-               uint64_t srio0:1;
-               uint64_t pem1:1;
-               uint64_t pem0:1;
-               uint64_t ptp:1;
-               uint64_t agl:1;
-               uint64_t reserved_37_45:9;
-               uint64_t agx0:1;
-               uint64_t dpi:1;
-               uint64_t sli:1;
-               uint64_t usb:1;
-               uint64_t dfa:1;
-               uint64_t key:1;
-               uint64_t rad:1;
-               uint64_t tim:1;
-               uint64_t zip:1;
-               uint64_t pko:1;
-               uint64_t pip:1;
-               uint64_t ipd:1;
-               uint64_t l2c:1;
-               uint64_t pow:1;
-               uint64_t fpa:1;
-               uint64_t iob:1;
-               uint64_t mio:1;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t wdog:16;
+       struct cvmx_ciu_qlm_dcok_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t qlm_dcok:4;
+#else
+               uint64_t qlm_dcok:4;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
-       struct cvmx_ciu_intx_en1_cn30xx {
-               uint64_t reserved_1_63:63;
-               uint64_t wdog:1;
-       } cn30xx;
-       struct cvmx_ciu_intx_en1_cn31xx {
+       struct cvmx_ciu_qlm_dcok_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_2_63:62;
-               uint64_t wdog:2;
-       } cn31xx;
-       struct cvmx_ciu_intx_en1_cn38xx {
-               uint64_t reserved_16_63:48;
-               uint64_t wdog:16;
-       } cn38xx;
-       struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
-       struct cvmx_ciu_intx_en1_cn31xx cn50xx;
-       struct cvmx_ciu_intx_en1_cn52xx {
-               uint64_t reserved_20_63:44;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t reserved_4_15:12;
-               uint64_t wdog:4;
+               uint64_t qlm_dcok:2;
+#else
+               uint64_t qlm_dcok:2;
+               uint64_t reserved_2_63:62;
+#endif
        } cn52xx;
-       struct cvmx_ciu_intx_en1_cn52xxp1 {
-               uint64_t reserved_19_63:45;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t reserved_4_15:12;
-               uint64_t wdog:4;
-       } cn52xxp1;
-       struct cvmx_ciu_intx_en1_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t wdog:12;
+       struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
+       struct cvmx_ciu_qlm_dcok_s cn56xx;
+       struct cvmx_ciu_qlm_dcok_s cn56xxp1;
+};
+
+union cvmx_ciu_qlm_jtgc {
+       uint64_t u64;
+       struct cvmx_ciu_qlm_jtgc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_17_63:47;
+               uint64_t bypass_ext:1;
+               uint64_t reserved_11_15:5;
+               uint64_t clk_div:3;
+               uint64_t reserved_7_7:1;
+               uint64_t mux_sel:3;
+               uint64_t bypass:4;
+#else
+               uint64_t bypass:4;
+               uint64_t mux_sel:3;
+               uint64_t reserved_7_7:1;
+               uint64_t clk_div:3;
+               uint64_t reserved_11_15:5;
+               uint64_t bypass_ext:1;
+               uint64_t reserved_17_63:47;
+#endif
+       } s;
+       struct cvmx_ciu_qlm_jtgc_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_11_63:53;
+               uint64_t clk_div:3;
+               uint64_t reserved_5_7:3;
+               uint64_t mux_sel:1;
+               uint64_t reserved_2_3:2;
+               uint64_t bypass:2;
+#else
+               uint64_t bypass:2;
+               uint64_t reserved_2_3:2;
+               uint64_t mux_sel:1;
+               uint64_t reserved_5_7:3;
+               uint64_t clk_div:3;
+               uint64_t reserved_11_63:53;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
+       struct cvmx_ciu_qlm_jtgc_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_11_63:53;
+               uint64_t clk_div:3;
+               uint64_t reserved_6_7:2;
+               uint64_t mux_sel:2;
+               uint64_t bypass:4;
+#else
+               uint64_t bypass:4;
+               uint64_t mux_sel:2;
+               uint64_t reserved_6_7:2;
+               uint64_t clk_div:3;
+               uint64_t reserved_11_63:53;
+#endif
        } cn56xx;
-       struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
-       struct cvmx_ciu_intx_en1_cn38xx cn58xx;
-       struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
-       struct cvmx_ciu_intx_en1_cn63xx {
-               uint64_t rst:1;
-               uint64_t reserved_57_62:6;
-               uint64_t dfm:1;
-               uint64_t reserved_53_55:3;
-               uint64_t lmc0:1;
-               uint64_t srio1:1;
-               uint64_t srio0:1;
-               uint64_t pem1:1;
-               uint64_t pem0:1;
-               uint64_t ptp:1;
-               uint64_t agl:1;
-               uint64_t reserved_37_45:9;
-               uint64_t agx0:1;
-               uint64_t dpi:1;
-               uint64_t sli:1;
-               uint64_t usb:1;
-               uint64_t dfa:1;
-               uint64_t key:1;
-               uint64_t rad:1;
-               uint64_t tim:1;
-               uint64_t zip:1;
-               uint64_t pko:1;
-               uint64_t pip:1;
-               uint64_t ipd:1;
-               uint64_t l2c:1;
-               uint64_t pow:1;
-               uint64_t fpa:1;
-               uint64_t iob:1;
-               uint64_t mio:1;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t reserved_6_17:12;
-               uint64_t wdog:6;
-       } cn63xx;
-       struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
+       struct cvmx_ciu_qlm_jtgc_cn56xx cn56xxp1;
+       struct cvmx_ciu_qlm_jtgc_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_11_63:53;
+               uint64_t clk_div:3;
+               uint64_t reserved_6_7:2;
+               uint64_t mux_sel:2;
+               uint64_t reserved_3_3:1;
+               uint64_t bypass:3;
+#else
+               uint64_t bypass:3;
+               uint64_t reserved_3_3:1;
+               uint64_t mux_sel:2;
+               uint64_t reserved_6_7:2;
+               uint64_t clk_div:3;
+               uint64_t reserved_11_63:53;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_qlm_jtgc_cn61xx cn63xx;
+       struct cvmx_ciu_qlm_jtgc_cn61xx cn63xxp1;
+       struct cvmx_ciu_qlm_jtgc_cn61xx cn66xx;
+       struct cvmx_ciu_qlm_jtgc_s cn68xx;
+       struct cvmx_ciu_qlm_jtgc_s cn68xxp1;
+       struct cvmx_ciu_qlm_jtgc_cn61xx cnf71xx;
 };
 
-union cvmx_ciu_intx_en1_w1c {
+union cvmx_ciu_qlm_jtgd {
        uint64_t u64;
-       struct cvmx_ciu_intx_en1_w1c_s {
-               uint64_t rst:1;
-               uint64_t reserved_57_62:6;
-               uint64_t dfm:1;
-               uint64_t reserved_53_55:3;
-               uint64_t lmc0:1;
-               uint64_t srio1:1;
-               uint64_t srio0:1;
-               uint64_t pem1:1;
-               uint64_t pem0:1;
-               uint64_t ptp:1;
-               uint64_t agl:1;
-               uint64_t reserved_37_45:9;
-               uint64_t agx0:1;
-               uint64_t dpi:1;
-               uint64_t sli:1;
-               uint64_t usb:1;
-               uint64_t dfa:1;
-               uint64_t key:1;
-               uint64_t rad:1;
-               uint64_t tim:1;
-               uint64_t zip:1;
-               uint64_t pko:1;
-               uint64_t pip:1;
-               uint64_t ipd:1;
-               uint64_t l2c:1;
-               uint64_t pow:1;
-               uint64_t fpa:1;
-               uint64_t iob:1;
-               uint64_t mio:1;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t wdog:16;
+       struct cvmx_ciu_qlm_jtgd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t capture:1;
+               uint64_t shift:1;
+               uint64_t update:1;
+               uint64_t reserved_45_60:16;
+               uint64_t select:5;
+               uint64_t reserved_37_39:3;
+               uint64_t shft_cnt:5;
+               uint64_t shft_reg:32;
+#else
+               uint64_t shft_reg:32;
+               uint64_t shft_cnt:5;
+               uint64_t reserved_37_39:3;
+               uint64_t select:5;
+               uint64_t reserved_45_60:16;
+               uint64_t update:1;
+               uint64_t shift:1;
+               uint64_t capture:1;
+#endif
        } s;
-       struct cvmx_ciu_intx_en1_w1c_cn52xx {
-               uint64_t reserved_20_63:44;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t reserved_4_15:12;
-               uint64_t wdog:4;
+       struct cvmx_ciu_qlm_jtgd_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t capture:1;
+               uint64_t shift:1;
+               uint64_t update:1;
+               uint64_t reserved_42_60:19;
+               uint64_t select:2;
+               uint64_t reserved_37_39:3;
+               uint64_t shft_cnt:5;
+               uint64_t shft_reg:32;
+#else
+               uint64_t shft_reg:32;
+               uint64_t shft_cnt:5;
+               uint64_t reserved_37_39:3;
+               uint64_t select:2;
+               uint64_t reserved_42_60:19;
+               uint64_t update:1;
+               uint64_t shift:1;
+               uint64_t capture:1;
+#endif
        } cn52xx;
-       struct cvmx_ciu_intx_en1_w1c_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t wdog:12;
+       struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
+       struct cvmx_ciu_qlm_jtgd_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t capture:1;
+               uint64_t shift:1;
+               uint64_t update:1;
+               uint64_t reserved_44_60:17;
+               uint64_t select:4;
+               uint64_t reserved_37_39:3;
+               uint64_t shft_cnt:5;
+               uint64_t shft_reg:32;
+#else
+               uint64_t shft_reg:32;
+               uint64_t shft_cnt:5;
+               uint64_t reserved_37_39:3;
+               uint64_t select:4;
+               uint64_t reserved_44_60:17;
+               uint64_t update:1;
+               uint64_t shift:1;
+               uint64_t capture:1;
+#endif
        } cn56xx;
-       struct cvmx_ciu_intx_en1_w1c_cn58xx {
-               uint64_t reserved_16_63:48;
-               uint64_t wdog:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_en1_w1c_cn63xx {
-               uint64_t rst:1;
-               uint64_t reserved_57_62:6;
-               uint64_t dfm:1;
-               uint64_t reserved_53_55:3;
-               uint64_t lmc0:1;
-               uint64_t srio1:1;
-               uint64_t srio0:1;
-               uint64_t pem1:1;
-               uint64_t pem0:1;
-               uint64_t ptp:1;
-               uint64_t agl:1;
-               uint64_t reserved_37_45:9;
-               uint64_t agx0:1;
-               uint64_t dpi:1;
-               uint64_t sli:1;
-               uint64_t usb:1;
-               uint64_t dfa:1;
-               uint64_t key:1;
-               uint64_t rad:1;
-               uint64_t tim:1;
-               uint64_t zip:1;
-               uint64_t pko:1;
-               uint64_t pip:1;
-               uint64_t ipd:1;
-               uint64_t l2c:1;
-               uint64_t pow:1;
-               uint64_t fpa:1;
-               uint64_t iob:1;
-               uint64_t mio:1;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t reserved_6_17:12;
-               uint64_t wdog:6;
-       } cn63xx;
-       struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
+       struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t capture:1;
+               uint64_t shift:1;
+               uint64_t update:1;
+               uint64_t reserved_37_60:24;
+               uint64_t shft_cnt:5;
+               uint64_t shft_reg:32;
+#else
+               uint64_t shft_reg:32;
+               uint64_t shft_cnt:5;
+               uint64_t reserved_37_60:24;
+               uint64_t update:1;
+               uint64_t shift:1;
+               uint64_t capture:1;
+#endif
+       } cn56xxp1;
+       struct cvmx_ciu_qlm_jtgd_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t capture:1;
+               uint64_t shift:1;
+               uint64_t update:1;
+               uint64_t reserved_43_60:18;
+               uint64_t select:3;
+               uint64_t reserved_37_39:3;
+               uint64_t shft_cnt:5;
+               uint64_t shft_reg:32;
+#else
+               uint64_t shft_reg:32;
+               uint64_t shft_cnt:5;
+               uint64_t reserved_37_39:3;
+               uint64_t select:3;
+               uint64_t reserved_43_60:18;
+               uint64_t update:1;
+               uint64_t shift:1;
+               uint64_t capture:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_qlm_jtgd_cn61xx cn63xx;
+       struct cvmx_ciu_qlm_jtgd_cn61xx cn63xxp1;
+       struct cvmx_ciu_qlm_jtgd_cn61xx cn66xx;
+       struct cvmx_ciu_qlm_jtgd_s cn68xx;
+       struct cvmx_ciu_qlm_jtgd_s cn68xxp1;
+       struct cvmx_ciu_qlm_jtgd_cn61xx cnf71xx;
 };
 
-union cvmx_ciu_intx_en1_w1s {
+union cvmx_ciu_soft_bist {
        uint64_t u64;
-       struct cvmx_ciu_intx_en1_w1s_s {
-               uint64_t rst:1;
-               uint64_t reserved_57_62:6;
-               uint64_t dfm:1;
-               uint64_t reserved_53_55:3;
-               uint64_t lmc0:1;
-               uint64_t srio1:1;
-               uint64_t srio0:1;
-               uint64_t pem1:1;
-               uint64_t pem0:1;
-               uint64_t ptp:1;
-               uint64_t agl:1;
-               uint64_t reserved_37_45:9;
-               uint64_t agx0:1;
-               uint64_t dpi:1;
-               uint64_t sli:1;
-               uint64_t usb:1;
-               uint64_t dfa:1;
-               uint64_t key:1;
-               uint64_t rad:1;
-               uint64_t tim:1;
-               uint64_t zip:1;
-               uint64_t pko:1;
-               uint64_t pip:1;
-               uint64_t ipd:1;
-               uint64_t l2c:1;
-               uint64_t pow:1;
-               uint64_t fpa:1;
-               uint64_t iob:1;
-               uint64_t mio:1;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t wdog:16;
+       struct cvmx_ciu_soft_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t soft_bist:1;
+#else
+               uint64_t soft_bist:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
-       struct cvmx_ciu_intx_en1_w1s_cn52xx {
-               uint64_t reserved_20_63:44;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t reserved_4_15:12;
-               uint64_t wdog:4;
-       } cn52xx;
-       struct cvmx_ciu_intx_en1_w1s_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t wdog:12;
-       } cn56xx;
-       struct cvmx_ciu_intx_en1_w1s_cn58xx {
-               uint64_t reserved_16_63:48;
-               uint64_t wdog:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_en1_w1s_cn63xx {
-               uint64_t rst:1;
-               uint64_t reserved_57_62:6;
-               uint64_t dfm:1;
-               uint64_t reserved_53_55:3;
-               uint64_t lmc0:1;
-               uint64_t srio1:1;
-               uint64_t srio0:1;
-               uint64_t pem1:1;
-               uint64_t pem0:1;
-               uint64_t ptp:1;
-               uint64_t agl:1;
-               uint64_t reserved_37_45:9;
-               uint64_t agx0:1;
-               uint64_t dpi:1;
-               uint64_t sli:1;
-               uint64_t usb:1;
-               uint64_t dfa:1;
-               uint64_t key:1;
-               uint64_t rad:1;
-               uint64_t tim:1;
-               uint64_t zip:1;
-               uint64_t pko:1;
-               uint64_t pip:1;
-               uint64_t ipd:1;
-               uint64_t l2c:1;
-               uint64_t pow:1;
-               uint64_t fpa:1;
-               uint64_t iob:1;
-               uint64_t mio:1;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t reserved_6_17:12;
-               uint64_t wdog:6;
-       } cn63xx;
-       struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
+       struct cvmx_ciu_soft_bist_s cn30xx;
+       struct cvmx_ciu_soft_bist_s cn31xx;
+       struct cvmx_ciu_soft_bist_s cn38xx;
+       struct cvmx_ciu_soft_bist_s cn38xxp2;
+       struct cvmx_ciu_soft_bist_s cn50xx;
+       struct cvmx_ciu_soft_bist_s cn52xx;
+       struct cvmx_ciu_soft_bist_s cn52xxp1;
+       struct cvmx_ciu_soft_bist_s cn56xx;
+       struct cvmx_ciu_soft_bist_s cn56xxp1;
+       struct cvmx_ciu_soft_bist_s cn58xx;
+       struct cvmx_ciu_soft_bist_s cn58xxp1;
+       struct cvmx_ciu_soft_bist_s cn61xx;
+       struct cvmx_ciu_soft_bist_s cn63xx;
+       struct cvmx_ciu_soft_bist_s cn63xxp1;
+       struct cvmx_ciu_soft_bist_s cn66xx;
+       struct cvmx_ciu_soft_bist_s cn68xx;
+       struct cvmx_ciu_soft_bist_s cn68xxp1;
+       struct cvmx_ciu_soft_bist_s cnf71xx;
 };
 
-union cvmx_ciu_intx_en4_0 {
+union cvmx_ciu_soft_prst {
        uint64_t u64;
-       struct cvmx_ciu_intx_en4_0_s {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t mpi:1;
-               uint64_t pcm:1;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
+       struct cvmx_ciu_soft_prst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_3_63:61;
+               uint64_t host64:1;
+               uint64_t npi:1;
+               uint64_t soft_prst:1;
+#else
+               uint64_t soft_prst:1;
+               uint64_t npi:1;
+               uint64_t host64:1;
+               uint64_t reserved_3_63:61;
+#endif
        } s;
-       struct cvmx_ciu_intx_en4_0_cn50xx {
-               uint64_t reserved_59_63:5;
-               uint64_t mpi:1;
-               uint64_t pcm:1;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t reserved_47_47:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn50xx;
-       struct cvmx_ciu_intx_en4_0_cn52xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn52xx;
-       struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
-       struct cvmx_ciu_intx_en4_0_cn56xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn56xx;
-       struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
-       struct cvmx_ciu_intx_en4_0_cn58xx {
-               uint64_t reserved_56_63:8;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
-       struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
-       struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
+       struct cvmx_ciu_soft_prst_s cn30xx;
+       struct cvmx_ciu_soft_prst_s cn31xx;
+       struct cvmx_ciu_soft_prst_s cn38xx;
+       struct cvmx_ciu_soft_prst_s cn38xxp2;
+       struct cvmx_ciu_soft_prst_s cn50xx;
+       struct cvmx_ciu_soft_prst_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t soft_prst:1;
+#else
+               uint64_t soft_prst:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } cn52xx;
+       struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
+       struct cvmx_ciu_soft_prst_cn52xx cn56xx;
+       struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
+       struct cvmx_ciu_soft_prst_s cn58xx;
+       struct cvmx_ciu_soft_prst_s cn58xxp1;
+       struct cvmx_ciu_soft_prst_cn52xx cn61xx;
+       struct cvmx_ciu_soft_prst_cn52xx cn63xx;
+       struct cvmx_ciu_soft_prst_cn52xx cn63xxp1;
+       struct cvmx_ciu_soft_prst_cn52xx cn66xx;
+       struct cvmx_ciu_soft_prst_cn52xx cn68xx;
+       struct cvmx_ciu_soft_prst_cn52xx cn68xxp1;
+       struct cvmx_ciu_soft_prst_cn52xx cnf71xx;
 };
 
-union cvmx_ciu_intx_en4_0_w1c {
+union cvmx_ciu_soft_prst1 {
        uint64_t u64;
-       struct cvmx_ciu_intx_en4_0_w1c_s {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
+       struct cvmx_ciu_soft_prst1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t soft_prst:1;
+#else
+               uint64_t soft_prst:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
-       struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn52xx;
-       struct cvmx_ciu_intx_en4_0_w1c_s cn56xx;
-       struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
-               uint64_t reserved_56_63:8;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
-       struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
+       struct cvmx_ciu_soft_prst1_s cn52xx;
+       struct cvmx_ciu_soft_prst1_s cn52xxp1;
+       struct cvmx_ciu_soft_prst1_s cn56xx;
+       struct cvmx_ciu_soft_prst1_s cn56xxp1;
+       struct cvmx_ciu_soft_prst1_s cn61xx;
+       struct cvmx_ciu_soft_prst1_s cn63xx;
+       struct cvmx_ciu_soft_prst1_s cn63xxp1;
+       struct cvmx_ciu_soft_prst1_s cn66xx;
+       struct cvmx_ciu_soft_prst1_s cn68xx;
+       struct cvmx_ciu_soft_prst1_s cn68xxp1;
+       struct cvmx_ciu_soft_prst1_s cnf71xx;
 };
 
-union cvmx_ciu_intx_en4_0_w1s {
+union cvmx_ciu_soft_prst2 {
        uint64_t u64;
-       struct cvmx_ciu_intx_en4_0_w1s_s {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
+       struct cvmx_ciu_soft_prst2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t soft_prst:1;
+#else
+               uint64_t soft_prst:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
-       struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn52xx;
-       struct cvmx_ciu_intx_en4_0_w1s_s cn56xx;
-       struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
-               uint64_t reserved_56_63:8;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t reserved_44_44:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
-       struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
+       struct cvmx_ciu_soft_prst2_s cn66xx;
 };
 
-union cvmx_ciu_intx_en4_1 {
+union cvmx_ciu_soft_prst3 {
        uint64_t u64;
-       struct cvmx_ciu_intx_en4_1_s {
+       struct cvmx_ciu_soft_prst3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t soft_prst:1;
+#else
+               uint64_t soft_prst:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } s;
+       struct cvmx_ciu_soft_prst3_s cn66xx;
+};
+
+union cvmx_ciu_soft_rst {
+       uint64_t u64;
+       struct cvmx_ciu_soft_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t soft_rst:1;
+#else
+               uint64_t soft_rst:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } s;
+       struct cvmx_ciu_soft_rst_s cn30xx;
+       struct cvmx_ciu_soft_rst_s cn31xx;
+       struct cvmx_ciu_soft_rst_s cn38xx;
+       struct cvmx_ciu_soft_rst_s cn38xxp2;
+       struct cvmx_ciu_soft_rst_s cn50xx;
+       struct cvmx_ciu_soft_rst_s cn52xx;
+       struct cvmx_ciu_soft_rst_s cn52xxp1;
+       struct cvmx_ciu_soft_rst_s cn56xx;
+       struct cvmx_ciu_soft_rst_s cn56xxp1;
+       struct cvmx_ciu_soft_rst_s cn58xx;
+       struct cvmx_ciu_soft_rst_s cn58xxp1;
+       struct cvmx_ciu_soft_rst_s cn61xx;
+       struct cvmx_ciu_soft_rst_s cn63xx;
+       struct cvmx_ciu_soft_rst_s cn63xxp1;
+       struct cvmx_ciu_soft_rst_s cn66xx;
+       struct cvmx_ciu_soft_rst_s cn68xx;
+       struct cvmx_ciu_soft_rst_s cn68xxp1;
+       struct cvmx_ciu_soft_rst_s cnf71xx;
+};
+
+union cvmx_ciu_sum1_iox_int {
+       uint64_t u64;
+       struct cvmx_ciu_sum1_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t rst:1;
-               uint64_t reserved_57_62:6;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
                uint64_t dfm:1;
                uint64_t reserved_53_55:3;
                uint64_t lmc0:1;
-               uint64_t srio1:1;
-               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu_sum1_iox_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
                uint64_t pem1:1;
                uint64_t pem0:1;
                uint64_t ptp:1;
                uint64_t agl:1;
-               uint64_t reserved_37_45:9;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
                uint64_t agx0:1;
                uint64_t dpi:1;
                uint64_t sli:1;
@@ -1116,54 +8685,62 @@ union cvmx_ciu_intx_en4_1 {
                uint64_t mio:1;
                uint64_t nand:1;
                uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t wdog:16;
-       } s;
-       struct cvmx_ciu_intx_en4_1_cn50xx {
-               uint64_t reserved_2_63:62;
-               uint64_t wdog:2;
-       } cn50xx;
-       struct cvmx_ciu_intx_en4_1_cn52xx {
-               uint64_t reserved_20_63:44;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t reserved_4_15:12;
+               uint64_t reserved_4_17:14;
                uint64_t wdog:4;
-       } cn52xx;
-       struct cvmx_ciu_intx_en4_1_cn52xxp1 {
-               uint64_t reserved_19_63:45;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t reserved_4_15:12;
+#else
                uint64_t wdog:4;
-       } cn52xxp1;
-       struct cvmx_ciu_intx_en4_1_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t wdog:12;
-       } cn56xx;
-       struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
-       struct cvmx_ciu_intx_en4_1_cn58xx {
-               uint64_t reserved_16_63:48;
-               uint64_t wdog:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
-       struct cvmx_ciu_intx_en4_1_cn63xx {
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
                uint64_t rst:1;
-               uint64_t reserved_57_62:6;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_sum1_iox_int_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
                uint64_t dfm:1;
                uint64_t reserved_53_55:3;
                uint64_t lmc0:1;
-               uint64_t srio1:1;
+               uint64_t reserved_51_51:1;
                uint64_t srio0:1;
                uint64_t pem1:1;
                uint64_t pem0:1;
                uint64_t ptp:1;
                uint64_t agl:1;
-               uint64_t reserved_37_45:9;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
                uint64_t agx0:1;
                uint64_t dpi:1;
                uint64_t sli:1;
@@ -1183,36 +8760,69 @@ union cvmx_ciu_intx_en4_1 {
                uint64_t mio:1;
                uint64_t nand:1;
                uint64_t mii1:1;
-               uint64_t reserved_6_17:12;
-               uint64_t wdog:6;
-       } cn63xx;
-       struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
-};
-
-union cvmx_ciu_intx_en4_1_w1c {
-       uint64_t u64;
-       struct cvmx_ciu_intx_en4_1_w1c_s {
-               uint64_t rst:1;
-               uint64_t reserved_57_62:6;
-               uint64_t dfm:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
                uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_sum1_iox_int_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
                uint64_t lmc0:1;
-               uint64_t srio1:1;
-               uint64_t srio0:1;
+               uint64_t reserved_50_51:2;
                uint64_t pem1:1;
                uint64_t pem0:1;
                uint64_t ptp:1;
-               uint64_t agl:1;
-               uint64_t reserved_37_45:9;
+               uint64_t reserved_41_46:6;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
                uint64_t agx0:1;
                uint64_t dpi:1;
                uint64_t sli:1;
                uint64_t usb:1;
-               uint64_t dfa:1;
+               uint64_t reserved_32_32:1;
                uint64_t key:1;
                uint64_t rad:1;
                uint64_t tim:1;
-               uint64_t zip:1;
+               uint64_t reserved_28_28:1;
                uint64_t pko:1;
                uint64_t pip:1;
                uint64_t ipd:1;
@@ -1222,41 +8832,65 @@ union cvmx_ciu_intx_en4_1_w1c {
                uint64_t iob:1;
                uint64_t mio:1;
                uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t wdog:16;
-       } s;
-       struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
-               uint64_t reserved_20_63:44;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t reserved_4_15:12;
+               uint64_t reserved_4_18:15;
                uint64_t wdog:4;
-       } cn52xx;
-       struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t wdog:12;
-       } cn56xx;
-       struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
-               uint64_t reserved_16_63:48;
-               uint64_t wdog:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_46:6;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
                uint64_t rst:1;
-               uint64_t reserved_57_62:6;
+#endif
+       } cnf71xx;
+};
+
+union cvmx_ciu_sum1_ppx_ip2 {
+       uint64_t u64;
+       struct cvmx_ciu_sum1_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
                uint64_t dfm:1;
                uint64_t reserved_53_55:3;
                uint64_t lmc0:1;
-               uint64_t srio1:1;
+               uint64_t reserved_51_51:1;
                uint64_t srio0:1;
                uint64_t pem1:1;
                uint64_t pem0:1;
                uint64_t ptp:1;
                uint64_t agl:1;
-               uint64_t reserved_37_45:9;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
                uint64_t agx0:1;
                uint64_t dpi:1;
                uint64_t sli:1;
@@ -1276,27 +8910,64 @@ union cvmx_ciu_intx_en4_1_w1c {
                uint64_t mio:1;
                uint64_t nand:1;
                uint64_t mii1:1;
-               uint64_t reserved_6_17:12;
-               uint64_t wdog:6;
-       } cn63xx;
-       struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
-};
-
-union cvmx_ciu_intx_en4_1_w1s {
-       uint64_t u64;
-       struct cvmx_ciu_intx_en4_1_w1s_s {
-               uint64_t rst:1;
-               uint64_t reserved_57_62:6;
-               uint64_t dfm:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
                uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu_sum1_ppx_ip2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
                uint64_t lmc0:1;
-               uint64_t srio1:1;
-               uint64_t srio0:1;
+               uint64_t reserved_50_51:2;
                uint64_t pem1:1;
                uint64_t pem0:1;
                uint64_t ptp:1;
                uint64_t agl:1;
-               uint64_t reserved_37_45:9;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
                uint64_t agx0:1;
                uint64_t dpi:1;
                uint64_t sli:1;
@@ -1316,40 +8987,62 @@ union cvmx_ciu_intx_en4_1_w1s {
                uint64_t mio:1;
                uint64_t nand:1;
                uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t wdog:16;
-       } s;
-       struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
-               uint64_t reserved_20_63:44;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t reserved_4_15:12;
+               uint64_t reserved_4_17:14;
                uint64_t wdog:4;
-       } cn52xx;
-       struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t wdog:12;
-       } cn56xx;
-       struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
-               uint64_t reserved_16_63:48;
-               uint64_t wdog:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
                uint64_t rst:1;
-               uint64_t reserved_57_62:6;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_sum1_ppx_ip2_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
                uint64_t dfm:1;
                uint64_t reserved_53_55:3;
                uint64_t lmc0:1;
-               uint64_t srio1:1;
+               uint64_t reserved_51_51:1;
                uint64_t srio0:1;
                uint64_t pem1:1;
                uint64_t pem0:1;
                uint64_t ptp:1;
                uint64_t agl:1;
-               uint64_t reserved_37_45:9;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
                uint64_t agx0:1;
                uint64_t dpi:1;
                uint64_t sli:1;
@@ -1369,330 +9062,289 @@ union cvmx_ciu_intx_en4_1_w1s {
                uint64_t mio:1;
                uint64_t nand:1;
                uint64_t mii1:1;
-               uint64_t reserved_6_17:12;
-               uint64_t wdog:6;
-       } cn63xx;
-       struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
-};
-
-union cvmx_ciu_intx_sum0 {
-       uint64_t u64;
-       struct cvmx_ciu_intx_sum0_s {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t mpi:1;
-               uint64_t pcm:1;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } s;
-       struct cvmx_ciu_intx_sum0_cn30xx {
-               uint64_t reserved_59_63:5;
-               uint64_t mpi:1;
-               uint64_t pcm:1;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t reserved_47_47:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn30xx;
-       struct cvmx_ciu_intx_sum0_cn31xx {
-               uint64_t reserved_59_63:5;
-               uint64_t mpi:1;
-               uint64_t pcm:1;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn31xx;
-       struct cvmx_ciu_intx_sum0_cn38xx {
-               uint64_t reserved_56_63:8;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn38xx;
-       struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
-       struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
-       struct cvmx_ciu_intx_sum0_cn52xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn52xx;
-       struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
-       struct cvmx_ciu_intx_sum0_cn56xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn56xx;
-       struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
-       struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
-       struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
-       struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
-       struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
-};
-
-union cvmx_ciu_intx_sum4 {
-       uint64_t u64;
-       struct cvmx_ciu_intx_sum4_s {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t mpi:1;
-               uint64_t pcm:1;
-               uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } s;
-       struct cvmx_ciu_intx_sum4_cn50xx {
-               uint64_t reserved_59_63:5;
-               uint64_t mpi:1;
-               uint64_t pcm:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
                uint64_t usb:1;
-               uint64_t timer:4;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
                uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t reserved_47_47:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn50xx;
-       struct cvmx_ciu_intx_sum4_cn52xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_sum1_ppx_ip2_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t reserved_41_46:6;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
                uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn52xx;
-       struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
-       struct cvmx_ciu_intx_sum4_cn56xx {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
+               uint64_t reserved_32_32:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_28_28:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_4_18:15;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
                uint64_t usb:1;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn56xx;
-       struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
-       struct cvmx_ciu_intx_sum4_cn58xx {
-               uint64_t reserved_56_63:8;
-               uint64_t timer:4;
-               uint64_t key_zero:1;
-               uint64_t ipd_drp:1;
-               uint64_t gmx_drp:2;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } cn58xx;
-       struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
-       struct cvmx_ciu_intx_sum4_cn52xx cn63xx;
-       struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_46:6;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cnf71xx;
 };
 
-union cvmx_ciu_int33_sum0 {
+union cvmx_ciu_sum1_ppx_ip3 {
        uint64_t u64;
-       struct cvmx_ciu_int33_sum0_s {
-               uint64_t bootdma:1;
-               uint64_t mii:1;
-               uint64_t ipdppthr:1;
-               uint64_t powiq:1;
-               uint64_t twsi2:1;
-               uint64_t reserved_57_58:2;
+       struct cvmx_ciu_sum1_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
                uint64_t usb:1;
-               uint64_t timer:4;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
                uint64_t reserved_51_51:1;
-               uint64_t ipd_drp:1;
-               uint64_t reserved_49_49:1;
-               uint64_t gmx_drp:1;
-               uint64_t trace:1;
-               uint64_t rml:1;
-               uint64_t twsi:1;
-               uint64_t wdog_sum:1;
-               uint64_t pci_msi:4;
-               uint64_t pci_int:4;
-               uint64_t uart:2;
-               uint64_t mbox:2;
-               uint64_t gpio:16;
-               uint64_t workq:16;
-       } s;
-       struct cvmx_ciu_int33_sum0_s cn63xx;
-       struct cvmx_ciu_int33_sum0_s cn63xxp1;
-};
-
-union cvmx_ciu_int_dbg_sel {
-       uint64_t u64;
-       struct cvmx_ciu_int_dbg_sel_s {
-               uint64_t reserved_19_63:45;
-               uint64_t sel:3;
-               uint64_t reserved_10_15:6;
-               uint64_t irq:2;
-               uint64_t reserved_3_7:5;
-               uint64_t pp:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
        } s;
-       struct cvmx_ciu_int_dbg_sel_s cn63xx;
-};
-
-union cvmx_ciu_int_sum1 {
-       uint64_t u64;
-       struct cvmx_ciu_int_sum1_s {
+       struct cvmx_ciu_sum1_ppx_ip3_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t rst:1;
-               uint64_t reserved_57_62:6;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_4_17:14;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_sum1_ppx_ip3_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
                uint64_t dfm:1;
                uint64_t reserved_53_55:3;
                uint64_t lmc0:1;
-               uint64_t srio1:1;
+               uint64_t reserved_51_51:1;
                uint64_t srio0:1;
                uint64_t pem1:1;
                uint64_t pem0:1;
                uint64_t ptp:1;
                uint64_t agl:1;
-               uint64_t reserved_37_45:9;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
                uint64_t agx0:1;
                uint64_t dpi:1;
                uint64_t sli:1;
@@ -1712,70 +9364,69 @@ union cvmx_ciu_int_sum1 {
                uint64_t mio:1;
                uint64_t nand:1;
                uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t wdog:16;
-       } s;
-       struct cvmx_ciu_int_sum1_cn30xx {
-               uint64_t reserved_1_63:63;
-               uint64_t wdog:1;
-       } cn30xx;
-       struct cvmx_ciu_int_sum1_cn31xx {
-               uint64_t reserved_2_63:62;
-               uint64_t wdog:2;
-       } cn31xx;
-       struct cvmx_ciu_int_sum1_cn38xx {
-               uint64_t reserved_16_63:48;
-               uint64_t wdog:16;
-       } cn38xx;
-       struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
-       struct cvmx_ciu_int_sum1_cn31xx cn50xx;
-       struct cvmx_ciu_int_sum1_cn52xx {
-               uint64_t reserved_20_63:44;
-               uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t reserved_4_15:12;
-               uint64_t wdog:4;
-       } cn52xx;
-       struct cvmx_ciu_int_sum1_cn52xxp1 {
-               uint64_t reserved_19_63:45;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
                uint64_t mii1:1;
-               uint64_t usb1:1;
-               uint64_t uart2:1;
-               uint64_t reserved_4_15:12;
-               uint64_t wdog:4;
-       } cn52xxp1;
-       struct cvmx_ciu_int_sum1_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t wdog:12;
-       } cn56xx;
-       struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
-       struct cvmx_ciu_int_sum1_cn38xx cn58xx;
-       struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
-       struct cvmx_ciu_int_sum1_cn63xx {
-               uint64_t rst:1;
-               uint64_t reserved_57_62:6;
-               uint64_t dfm:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
                uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_sum1_ppx_ip3_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
                uint64_t lmc0:1;
-               uint64_t srio1:1;
-               uint64_t srio0:1;
+               uint64_t reserved_50_51:2;
                uint64_t pem1:1;
                uint64_t pem0:1;
                uint64_t ptp:1;
-               uint64_t agl:1;
-               uint64_t reserved_37_45:9;
+               uint64_t reserved_41_46:6;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
                uint64_t agx0:1;
                uint64_t dpi:1;
                uint64_t sli:1;
                uint64_t usb:1;
-               uint64_t dfa:1;
+               uint64_t reserved_32_32:1;
                uint64_t key:1;
                uint64_t rad:1;
                uint64_t tim:1;
-               uint64_t zip:1;
+               uint64_t reserved_28_28:1;
                uint64_t pko:1;
                uint64_t pip:1;
                uint64_t ipd:1;
@@ -1785,473 +9436,493 @@ union cvmx_ciu_int_sum1 {
                uint64_t iob:1;
                uint64_t mio:1;
                uint64_t nand:1;
-               uint64_t mii1:1;
-               uint64_t reserved_6_17:12;
-               uint64_t wdog:6;
-       } cn63xx;
-       struct cvmx_ciu_int_sum1_cn63xx cn63xxp1;
-};
-
-union cvmx_ciu_mbox_clrx {
-       uint64_t u64;
-       struct cvmx_ciu_mbox_clrx_s {
-               uint64_t reserved_32_63:32;
-               uint64_t bits:32;
-       } s;
-       struct cvmx_ciu_mbox_clrx_s cn30xx;
-       struct cvmx_ciu_mbox_clrx_s cn31xx;
-       struct cvmx_ciu_mbox_clrx_s cn38xx;
-       struct cvmx_ciu_mbox_clrx_s cn38xxp2;
-       struct cvmx_ciu_mbox_clrx_s cn50xx;
-       struct cvmx_ciu_mbox_clrx_s cn52xx;
-       struct cvmx_ciu_mbox_clrx_s cn52xxp1;
-       struct cvmx_ciu_mbox_clrx_s cn56xx;
-       struct cvmx_ciu_mbox_clrx_s cn56xxp1;
-       struct cvmx_ciu_mbox_clrx_s cn58xx;
-       struct cvmx_ciu_mbox_clrx_s cn58xxp1;
-       struct cvmx_ciu_mbox_clrx_s cn63xx;
-       struct cvmx_ciu_mbox_clrx_s cn63xxp1;
-};
-
-union cvmx_ciu_mbox_setx {
-       uint64_t u64;
-       struct cvmx_ciu_mbox_setx_s {
-               uint64_t reserved_32_63:32;
-               uint64_t bits:32;
-       } s;
-       struct cvmx_ciu_mbox_setx_s cn30xx;
-       struct cvmx_ciu_mbox_setx_s cn31xx;
-       struct cvmx_ciu_mbox_setx_s cn38xx;
-       struct cvmx_ciu_mbox_setx_s cn38xxp2;
-       struct cvmx_ciu_mbox_setx_s cn50xx;
-       struct cvmx_ciu_mbox_setx_s cn52xx;
-       struct cvmx_ciu_mbox_setx_s cn52xxp1;
-       struct cvmx_ciu_mbox_setx_s cn56xx;
-       struct cvmx_ciu_mbox_setx_s cn56xxp1;
-       struct cvmx_ciu_mbox_setx_s cn58xx;
-       struct cvmx_ciu_mbox_setx_s cn58xxp1;
-       struct cvmx_ciu_mbox_setx_s cn63xx;
-       struct cvmx_ciu_mbox_setx_s cn63xxp1;
-};
-
-union cvmx_ciu_nmi {
-       uint64_t u64;
-       struct cvmx_ciu_nmi_s {
-               uint64_t reserved_16_63:48;
-               uint64_t nmi:16;
-       } s;
-       struct cvmx_ciu_nmi_cn30xx {
-               uint64_t reserved_1_63:63;
-               uint64_t nmi:1;
-       } cn30xx;
-       struct cvmx_ciu_nmi_cn31xx {
-               uint64_t reserved_2_63:62;
-               uint64_t nmi:2;
-       } cn31xx;
-       struct cvmx_ciu_nmi_s cn38xx;
-       struct cvmx_ciu_nmi_s cn38xxp2;
-       struct cvmx_ciu_nmi_cn31xx cn50xx;
-       struct cvmx_ciu_nmi_cn52xx {
-               uint64_t reserved_4_63:60;
-               uint64_t nmi:4;
-       } cn52xx;
-       struct cvmx_ciu_nmi_cn52xx cn52xxp1;
-       struct cvmx_ciu_nmi_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t nmi:12;
-       } cn56xx;
-       struct cvmx_ciu_nmi_cn56xx cn56xxp1;
-       struct cvmx_ciu_nmi_s cn58xx;
-       struct cvmx_ciu_nmi_s cn58xxp1;
-       struct cvmx_ciu_nmi_cn63xx {
-               uint64_t reserved_6_63:58;
-               uint64_t nmi:6;
-       } cn63xx;
-       struct cvmx_ciu_nmi_cn63xx cn63xxp1;
-};
-
-union cvmx_ciu_pci_inta {
-       uint64_t u64;
-       struct cvmx_ciu_pci_inta_s {
-               uint64_t reserved_2_63:62;
-               uint64_t intr:2;
-       } s;
-       struct cvmx_ciu_pci_inta_s cn30xx;
-       struct cvmx_ciu_pci_inta_s cn31xx;
-       struct cvmx_ciu_pci_inta_s cn38xx;
-       struct cvmx_ciu_pci_inta_s cn38xxp2;
-       struct cvmx_ciu_pci_inta_s cn50xx;
-       struct cvmx_ciu_pci_inta_s cn52xx;
-       struct cvmx_ciu_pci_inta_s cn52xxp1;
-       struct cvmx_ciu_pci_inta_s cn56xx;
-       struct cvmx_ciu_pci_inta_s cn56xxp1;
-       struct cvmx_ciu_pci_inta_s cn58xx;
-       struct cvmx_ciu_pci_inta_s cn58xxp1;
-       struct cvmx_ciu_pci_inta_s cn63xx;
-       struct cvmx_ciu_pci_inta_s cn63xxp1;
-};
-
-union cvmx_ciu_pp_dbg {
-       uint64_t u64;
-       struct cvmx_ciu_pp_dbg_s {
-               uint64_t reserved_16_63:48;
-               uint64_t ppdbg:16;
-       } s;
-       struct cvmx_ciu_pp_dbg_cn30xx {
-               uint64_t reserved_1_63:63;
-               uint64_t ppdbg:1;
-       } cn30xx;
-       struct cvmx_ciu_pp_dbg_cn31xx {
-               uint64_t reserved_2_63:62;
-               uint64_t ppdbg:2;
-       } cn31xx;
-       struct cvmx_ciu_pp_dbg_s cn38xx;
-       struct cvmx_ciu_pp_dbg_s cn38xxp2;
-       struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
-       struct cvmx_ciu_pp_dbg_cn52xx {
-               uint64_t reserved_4_63:60;
-               uint64_t ppdbg:4;
-       } cn52xx;
-       struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
-       struct cvmx_ciu_pp_dbg_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t ppdbg:12;
-       } cn56xx;
-       struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
-       struct cvmx_ciu_pp_dbg_s cn58xx;
-       struct cvmx_ciu_pp_dbg_s cn58xxp1;
-       struct cvmx_ciu_pp_dbg_cn63xx {
-               uint64_t reserved_6_63:58;
-               uint64_t ppdbg:6;
-       } cn63xx;
-       struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1;
-};
-
-union cvmx_ciu_pp_pokex {
-       uint64_t u64;
-       struct cvmx_ciu_pp_pokex_s {
-               uint64_t poke:64;
-       } s;
-       struct cvmx_ciu_pp_pokex_s cn30xx;
-       struct cvmx_ciu_pp_pokex_s cn31xx;
-       struct cvmx_ciu_pp_pokex_s cn38xx;
-       struct cvmx_ciu_pp_pokex_s cn38xxp2;
-       struct cvmx_ciu_pp_pokex_s cn50xx;
-       struct cvmx_ciu_pp_pokex_s cn52xx;
-       struct cvmx_ciu_pp_pokex_s cn52xxp1;
-       struct cvmx_ciu_pp_pokex_s cn56xx;
-       struct cvmx_ciu_pp_pokex_s cn56xxp1;
-       struct cvmx_ciu_pp_pokex_s cn58xx;
-       struct cvmx_ciu_pp_pokex_s cn58xxp1;
-       struct cvmx_ciu_pp_pokex_s cn63xx;
-       struct cvmx_ciu_pp_pokex_s cn63xxp1;
-};
-
-union cvmx_ciu_pp_rst {
-       uint64_t u64;
-       struct cvmx_ciu_pp_rst_s {
-               uint64_t reserved_16_63:48;
-               uint64_t rst:15;
-               uint64_t rst0:1;
-       } s;
-       struct cvmx_ciu_pp_rst_cn30xx {
-               uint64_t reserved_1_63:63;
-               uint64_t rst0:1;
-       } cn30xx;
-       struct cvmx_ciu_pp_rst_cn31xx {
-               uint64_t reserved_2_63:62;
+               uint64_t reserved_4_18:15;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_46:6;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
                uint64_t rst:1;
-               uint64_t rst0:1;
-       } cn31xx;
-       struct cvmx_ciu_pp_rst_s cn38xx;
-       struct cvmx_ciu_pp_rst_s cn38xxp2;
-       struct cvmx_ciu_pp_rst_cn31xx cn50xx;
-       struct cvmx_ciu_pp_rst_cn52xx {
-               uint64_t reserved_4_63:60;
-               uint64_t rst:3;
-               uint64_t rst0:1;
-       } cn52xx;
-       struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
-       struct cvmx_ciu_pp_rst_cn56xx {
-               uint64_t reserved_12_63:52;
-               uint64_t rst:11;
-               uint64_t rst0:1;
-       } cn56xx;
-       struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
-       struct cvmx_ciu_pp_rst_s cn58xx;
-       struct cvmx_ciu_pp_rst_s cn58xxp1;
-       struct cvmx_ciu_pp_rst_cn63xx {
-               uint64_t reserved_6_63:58;
-               uint64_t rst:5;
-               uint64_t rst0:1;
-       } cn63xx;
-       struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
+#endif
+       } cnf71xx;
 };
 
-union cvmx_ciu_qlm0 {
+union cvmx_ciu_sum1_ppx_ip4 {
        uint64_t u64;
-       struct cvmx_ciu_qlm0_s {
-               uint64_t g2bypass:1;
-               uint64_t reserved_53_62:10;
-               uint64_t g2deemph:5;
-               uint64_t reserved_45_47:3;
-               uint64_t g2margin:5;
-               uint64_t reserved_32_39:8;
-               uint64_t txbypass:1;
-               uint64_t reserved_21_30:10;
-               uint64_t txdeemph:5;
-               uint64_t reserved_13_15:3;
-               uint64_t txmargin:5;
-               uint64_t reserved_4_7:4;
-               uint64_t lane_en:4;
+       struct cvmx_ciu_sum1_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
        } s;
-       struct cvmx_ciu_qlm0_s cn63xx;
-       struct cvmx_ciu_qlm0_cn63xxp1 {
-               uint64_t reserved_32_63:32;
-               uint64_t txbypass:1;
-               uint64_t reserved_20_30:11;
-               uint64_t txdeemph:4;
-               uint64_t reserved_13_15:3;
-               uint64_t txmargin:5;
-               uint64_t reserved_4_7:4;
-               uint64_t lane_en:4;
-       } cn63xxp1;
-};
-
-union cvmx_ciu_qlm1 {
-       uint64_t u64;
-       struct cvmx_ciu_qlm1_s {
-               uint64_t g2bypass:1;
+       struct cvmx_ciu_sum1_ppx_ip4_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
                uint64_t reserved_53_62:10;
-               uint64_t g2deemph:5;
-               uint64_t reserved_45_47:3;
-               uint64_t g2margin:5;
-               uint64_t reserved_32_39:8;
-               uint64_t txbypass:1;
-               uint64_t reserved_21_30:10;
-               uint64_t txdeemph:5;
-               uint64_t reserved_13_15:3;
-               uint64_t txmargin:5;
-               uint64_t reserved_4_7:4;
-               uint64_t lane_en:4;
-       } s;
-       struct cvmx_ciu_qlm1_s cn63xx;
-       struct cvmx_ciu_qlm1_cn63xxp1 {
-               uint64_t reserved_32_63:32;
-               uint64_t txbypass:1;
-               uint64_t reserved_20_30:11;
-               uint64_t txdeemph:4;
-               uint64_t reserved_13_15:3;
-               uint64_t txmargin:5;
-               uint64_t reserved_4_7:4;
-               uint64_t lane_en:4;
-       } cn63xxp1;
-};
-
-union cvmx_ciu_qlm2 {
-       uint64_t u64;
-       struct cvmx_ciu_qlm2_s {
-               uint64_t reserved_32_63:32;
-               uint64_t txbypass:1;
-               uint64_t reserved_21_30:10;
-               uint64_t txdeemph:5;
-               uint64_t reserved_13_15:3;
-               uint64_t txmargin:5;
-               uint64_t reserved_4_7:4;
-               uint64_t lane_en:4;
-       } s;
-       struct cvmx_ciu_qlm2_s cn63xx;
-       struct cvmx_ciu_qlm2_cn63xxp1 {
-               uint64_t reserved_32_63:32;
-               uint64_t txbypass:1;
-               uint64_t reserved_20_30:11;
-               uint64_t txdeemph:4;
-               uint64_t reserved_13_15:3;
-               uint64_t txmargin:5;
-               uint64_t reserved_4_7:4;
-               uint64_t lane_en:4;
-       } cn63xxp1;
-};
-
-union cvmx_ciu_qlm_dcok {
-       uint64_t u64;
-       struct cvmx_ciu_qlm_dcok_s {
-               uint64_t reserved_4_63:60;
-               uint64_t qlm_dcok:4;
-       } s;
-       struct cvmx_ciu_qlm_dcok_cn52xx {
-               uint64_t reserved_2_63:62;
-               uint64_t qlm_dcok:2;
-       } cn52xx;
-       struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
-       struct cvmx_ciu_qlm_dcok_s cn56xx;
-       struct cvmx_ciu_qlm_dcok_s cn56xxp1;
-};
-
-union cvmx_ciu_qlm_jtgc {
-       uint64_t u64;
-       struct cvmx_ciu_qlm_jtgc_s {
-               uint64_t reserved_11_63:53;
-               uint64_t clk_div:3;
-               uint64_t reserved_6_7:2;
-               uint64_t mux_sel:2;
-               uint64_t bypass:4;
-       } s;
-       struct cvmx_ciu_qlm_jtgc_cn52xx {
-               uint64_t reserved_11_63:53;
-               uint64_t clk_div:3;
-               uint64_t reserved_5_7:3;
-               uint64_t mux_sel:1;
-               uint64_t reserved_2_3:2;
-               uint64_t bypass:2;
-       } cn52xx;
-       struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
-       struct cvmx_ciu_qlm_jtgc_s cn56xx;
-       struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
-       struct cvmx_ciu_qlm_jtgc_cn63xx {
-               uint64_t reserved_11_63:53;
-               uint64_t clk_div:3;
-               uint64_t reserved_6_7:2;
-               uint64_t mux_sel:2;
-               uint64_t reserved_3_3:1;
-               uint64_t bypass:3;
-       } cn63xx;
-       struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1;
-};
-
-union cvmx_ciu_qlm_jtgd {
-       uint64_t u64;
-       struct cvmx_ciu_qlm_jtgd_s {
-               uint64_t capture:1;
-               uint64_t shift:1;
-               uint64_t update:1;
-               uint64_t reserved_44_60:17;
-               uint64_t select:4;
-               uint64_t reserved_37_39:3;
-               uint64_t shft_cnt:5;
-               uint64_t shft_reg:32;
-       } s;
-       struct cvmx_ciu_qlm_jtgd_cn52xx {
-               uint64_t capture:1;
-               uint64_t shift:1;
-               uint64_t update:1;
-               uint64_t reserved_42_60:19;
-               uint64_t select:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_41_45:5;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_38_39:2;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_4_17:14;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_17:14;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_39:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_45:5;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_sum1_ppx_ip4_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_62_62:1;
+               uint64_t srio3:1;
+               uint64_t srio2:1;
+               uint64_t reserved_57_59:3;
+               uint64_t dfm:1;
+               uint64_t reserved_53_55:3;
+               uint64_t lmc0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t srio0:1;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t agl:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agx1:1;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t dfa:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t zip:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t mii1:1;
+               uint64_t reserved_10_17:8;
+               uint64_t wdog:10;
+#else
+               uint64_t wdog:10;
+               uint64_t reserved_10_17:8;
+               uint64_t mii1:1;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t zip:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t dfa:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
+               uint64_t agx1:1;
+               uint64_t reserved_38_45:8;
+               uint64_t agl:1;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t srio0:1;
+               uint64_t reserved_51_51:1;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_55:3;
+               uint64_t dfm:1;
+               uint64_t reserved_57_59:3;
+               uint64_t srio2:1;
+               uint64_t srio3:1;
+               uint64_t reserved_62_62:1;
+               uint64_t rst:1;
+#endif
+       } cn66xx;
+       struct cvmx_ciu_sum1_ppx_ip4_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_53_62:10;
+               uint64_t lmc0:1;
+               uint64_t reserved_50_51:2;
+               uint64_t pem1:1;
+               uint64_t pem0:1;
+               uint64_t ptp:1;
+               uint64_t reserved_41_46:6;
+               uint64_t dpi_dma:1;
                uint64_t reserved_37_39:3;
-               uint64_t shft_cnt:5;
-               uint64_t shft_reg:32;
-       } cn52xx;
-       struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
-       struct cvmx_ciu_qlm_jtgd_s cn56xx;
-       struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
-               uint64_t capture:1;
-               uint64_t shift:1;
-               uint64_t update:1;
-               uint64_t reserved_37_60:24;
-               uint64_t shft_cnt:5;
-               uint64_t shft_reg:32;
-       } cn56xxp1;
-       struct cvmx_ciu_qlm_jtgd_cn63xx {
-               uint64_t capture:1;
-               uint64_t shift:1;
-               uint64_t update:1;
-               uint64_t reserved_43_60:18;
-               uint64_t select:3;
+               uint64_t agx0:1;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t usb:1;
+               uint64_t reserved_32_32:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_28_28:1;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t l2c:1;
+               uint64_t pow:1;
+               uint64_t fpa:1;
+               uint64_t iob:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_4_18:15;
+               uint64_t wdog:4;
+#else
+               uint64_t wdog:4;
+               uint64_t reserved_4_18:15;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t iob:1;
+               uint64_t fpa:1;
+               uint64_t pow:1;
+               uint64_t l2c:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_28_28:1;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_32_32:1;
+               uint64_t usb:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t agx0:1;
                uint64_t reserved_37_39:3;
-               uint64_t shft_cnt:5;
-               uint64_t shft_reg:32;
-       } cn63xx;
-       struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_41_46:6;
+               uint64_t ptp:1;
+               uint64_t pem0:1;
+               uint64_t pem1:1;
+               uint64_t reserved_50_51:2;
+               uint64_t lmc0:1;
+               uint64_t reserved_53_62:10;
+               uint64_t rst:1;
+#endif
+       } cnf71xx;
 };
 
-union cvmx_ciu_soft_bist {
+union cvmx_ciu_sum2_iox_int {
        uint64_t u64;
-       struct cvmx_ciu_soft_bist_s {
-               uint64_t reserved_1_63:63;
-               uint64_t soft_bist:1;
+       struct cvmx_ciu_sum2_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
        } s;
-       struct cvmx_ciu_soft_bist_s cn30xx;
-       struct cvmx_ciu_soft_bist_s cn31xx;
-       struct cvmx_ciu_soft_bist_s cn38xx;
-       struct cvmx_ciu_soft_bist_s cn38xxp2;
-       struct cvmx_ciu_soft_bist_s cn50xx;
-       struct cvmx_ciu_soft_bist_s cn52xx;
-       struct cvmx_ciu_soft_bist_s cn52xxp1;
-       struct cvmx_ciu_soft_bist_s cn56xx;
-       struct cvmx_ciu_soft_bist_s cn56xxp1;
-       struct cvmx_ciu_soft_bist_s cn58xx;
-       struct cvmx_ciu_soft_bist_s cn58xxp1;
-       struct cvmx_ciu_soft_bist_s cn63xx;
-       struct cvmx_ciu_soft_bist_s cn63xxp1;
+       struct cvmx_ciu_sum2_iox_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_sum2_iox_int_cn61xx cn66xx;
+       struct cvmx_ciu_sum2_iox_int_s cnf71xx;
 };
 
-union cvmx_ciu_soft_prst {
+union cvmx_ciu_sum2_ppx_ip2 {
        uint64_t u64;
-       struct cvmx_ciu_soft_prst_s {
-               uint64_t reserved_3_63:61;
-               uint64_t host64:1;
-               uint64_t npi:1;
-               uint64_t soft_prst:1;
+       struct cvmx_ciu_sum2_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
        } s;
-       struct cvmx_ciu_soft_prst_s cn30xx;
-       struct cvmx_ciu_soft_prst_s cn31xx;
-       struct cvmx_ciu_soft_prst_s cn38xx;
-       struct cvmx_ciu_soft_prst_s cn38xxp2;
-       struct cvmx_ciu_soft_prst_s cn50xx;
-       struct cvmx_ciu_soft_prst_cn52xx {
-               uint64_t reserved_1_63:63;
-               uint64_t soft_prst:1;
-       } cn52xx;
-       struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
-       struct cvmx_ciu_soft_prst_cn52xx cn56xx;
-       struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
-       struct cvmx_ciu_soft_prst_s cn58xx;
-       struct cvmx_ciu_soft_prst_s cn58xxp1;
-       struct cvmx_ciu_soft_prst_cn52xx cn63xx;
-       struct cvmx_ciu_soft_prst_cn52xx cn63xxp1;
+       struct cvmx_ciu_sum2_ppx_ip2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_sum2_ppx_ip2_cn61xx cn66xx;
+       struct cvmx_ciu_sum2_ppx_ip2_s cnf71xx;
 };
 
-union cvmx_ciu_soft_prst1 {
+union cvmx_ciu_sum2_ppx_ip3 {
        uint64_t u64;
-       struct cvmx_ciu_soft_prst1_s {
-               uint64_t reserved_1_63:63;
-               uint64_t soft_prst:1;
+       struct cvmx_ciu_sum2_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
        } s;
-       struct cvmx_ciu_soft_prst1_s cn52xx;
-       struct cvmx_ciu_soft_prst1_s cn52xxp1;
-       struct cvmx_ciu_soft_prst1_s cn56xx;
-       struct cvmx_ciu_soft_prst1_s cn56xxp1;
-       struct cvmx_ciu_soft_prst1_s cn63xx;
-       struct cvmx_ciu_soft_prst1_s cn63xxp1;
+       struct cvmx_ciu_sum2_ppx_ip3_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_sum2_ppx_ip3_cn61xx cn66xx;
+       struct cvmx_ciu_sum2_ppx_ip3_s cnf71xx;
 };
 
-union cvmx_ciu_soft_rst {
+union cvmx_ciu_sum2_ppx_ip4 {
        uint64_t u64;
-       struct cvmx_ciu_soft_rst_s {
-               uint64_t reserved_1_63:63;
-               uint64_t soft_rst:1;
+       struct cvmx_ciu_sum2_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_15_63:49;
+               uint64_t endor:2;
+               uint64_t eoi:1;
+               uint64_t reserved_10_11:2;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_11:2;
+               uint64_t eoi:1;
+               uint64_t endor:2;
+               uint64_t reserved_15_63:49;
+#endif
        } s;
-       struct cvmx_ciu_soft_rst_s cn30xx;
-       struct cvmx_ciu_soft_rst_s cn31xx;
-       struct cvmx_ciu_soft_rst_s cn38xx;
-       struct cvmx_ciu_soft_rst_s cn38xxp2;
-       struct cvmx_ciu_soft_rst_s cn50xx;
-       struct cvmx_ciu_soft_rst_s cn52xx;
-       struct cvmx_ciu_soft_rst_s cn52xxp1;
-       struct cvmx_ciu_soft_rst_s cn56xx;
-       struct cvmx_ciu_soft_rst_s cn56xxp1;
-       struct cvmx_ciu_soft_rst_s cn58xx;
-       struct cvmx_ciu_soft_rst_s cn58xxp1;
-       struct cvmx_ciu_soft_rst_s cn63xx;
-       struct cvmx_ciu_soft_rst_s cn63xxp1;
+       struct cvmx_ciu_sum2_ppx_ip4_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t timer:6;
+               uint64_t reserved_0_3:4;
+#else
+               uint64_t reserved_0_3:4;
+               uint64_t timer:6;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn61xx;
+       struct cvmx_ciu_sum2_ppx_ip4_cn61xx cn66xx;
+       struct cvmx_ciu_sum2_ppx_ip4_s cnf71xx;
 };
 
 union cvmx_ciu_timx {
        uint64_t u64;
        struct cvmx_ciu_timx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_37_63:27;
                uint64_t one_shot:1;
                uint64_t len:36;
+#else
+               uint64_t len:36;
+               uint64_t one_shot:1;
+               uint64_t reserved_37_63:27;
+#endif
        } s;
        struct cvmx_ciu_timx_s cn30xx;
        struct cvmx_ciu_timx_s cn31xx;
@@ -2264,13 +9935,35 @@ union cvmx_ciu_timx {
        struct cvmx_ciu_timx_s cn56xxp1;
        struct cvmx_ciu_timx_s cn58xx;
        struct cvmx_ciu_timx_s cn58xxp1;
+       struct cvmx_ciu_timx_s cn61xx;
        struct cvmx_ciu_timx_s cn63xx;
        struct cvmx_ciu_timx_s cn63xxp1;
+       struct cvmx_ciu_timx_s cn66xx;
+       struct cvmx_ciu_timx_s cn68xx;
+       struct cvmx_ciu_timx_s cn68xxp1;
+       struct cvmx_ciu_timx_s cnf71xx;
+};
+
+union cvmx_ciu_tim_multi_cast {
+       uint64_t u64;
+       struct cvmx_ciu_tim_multi_cast_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } s;
+       struct cvmx_ciu_tim_multi_cast_s cn61xx;
+       struct cvmx_ciu_tim_multi_cast_s cn66xx;
+       struct cvmx_ciu_tim_multi_cast_s cnf71xx;
 };
 
 union cvmx_ciu_wdogx {
        uint64_t u64;
        struct cvmx_ciu_wdogx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_46_63:18;
                uint64_t gstopen:1;
                uint64_t dstop:1;
@@ -2278,6 +9971,15 @@ union cvmx_ciu_wdogx {
                uint64_t len:16;
                uint64_t state:2;
                uint64_t mode:2;
+#else
+               uint64_t mode:2;
+               uint64_t state:2;
+               uint64_t len:16;
+               uint64_t cnt:24;
+               uint64_t dstop:1;
+               uint64_t gstopen:1;
+               uint64_t reserved_46_63:18;
+#endif
        } s;
        struct cvmx_ciu_wdogx_s cn30xx;
        struct cvmx_ciu_wdogx_s cn31xx;
@@ -2290,8 +9992,13 @@ union cvmx_ciu_wdogx {
        struct cvmx_ciu_wdogx_s cn56xxp1;
        struct cvmx_ciu_wdogx_s cn58xx;
        struct cvmx_ciu_wdogx_s cn58xxp1;
+       struct cvmx_ciu_wdogx_s cn61xx;
        struct cvmx_ciu_wdogx_s cn63xx;
        struct cvmx_ciu_wdogx_s cn63xxp1;
+       struct cvmx_ciu_wdogx_s cn66xx;
+       struct cvmx_ciu_wdogx_s cn68xx;
+       struct cvmx_ciu_wdogx_s cn68xxp1;
+       struct cvmx_ciu_wdogx_s cnf71xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h 
b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
new file mode 100644
index 0000000..148bc9a
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
@@ -0,0 +1,7108 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_CIU2_DEFS_H__
+#define __CVMX_CIU2_DEFS_H__
+
+#define CVMX_CIU2_ACK_IOX_INT(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_ACK_PPX_IP2(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_ACK_PPX_IP3(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_ACK_PPX_IP4(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_MBOX(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull))
+#define CVMX_CIU2_INTR_RAM_ECC_CTL (CVMX_ADD_IO_SEG(0x0001070100102010ull))
+#define CVMX_CIU2_INTR_RAM_ECC_ST (CVMX_ADD_IO_SEG(0x0001070100102018ull))
+#define CVMX_CIU2_INTR_SLOWDOWN (CVMX_ADD_IO_SEG(0x0001070100102000ull))
+#define CVMX_CIU2_MSIRED_PPX_IP2(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_MSIRED_PPX_IP3(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_MSIRED_PPX_IP4(block_id) 
(CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_MSI_RCVX(offset) (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + 
((offset) & 255) * 8)
+#define CVMX_CIU2_MSI_SELX(offset) (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + 
((offset) & 255) * 8)
+#define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_RAW_IOX_INT_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_RAW_IOX_INT_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_RAW_IOX_INT_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_RAW_IOX_INT_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_RAW_IOX_INT_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP2_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP2_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP3_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP3_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP4_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP4_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_SRC_IOX_INT_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_SRC_IOX_INT_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_SRC_IOX_INT_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_SRC_IOX_INT_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_SRC_IOX_INT_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP3_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP3_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP4_IO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP4_RML(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id) 
(CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SUM_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070100000800ull) 
+ ((offset) & 1) * 8)
+#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) 
+ ((offset) & 31) * 8)
+#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) 
+ ((offset) & 31) * 8)
+#define CVMX_CIU2_SUM_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070100000400ull) 
+ ((offset) & 31) * 8)
+
+union cvmx_ciu2_ack_iox_int {
+       uint64_t u64;
+       struct cvmx_ciu2_ack_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t ack:1;
+#else
+               uint64_t ack:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } s;
+       struct cvmx_ciu2_ack_iox_int_s cn68xx;
+       struct cvmx_ciu2_ack_iox_int_s cn68xxp1;
+};
+
+union cvmx_ciu2_ack_ppx_ip2 {
+       uint64_t u64;
+       struct cvmx_ciu2_ack_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t ack:1;
+#else
+               uint64_t ack:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } s;
+       struct cvmx_ciu2_ack_ppx_ip2_s cn68xx;
+       struct cvmx_ciu2_ack_ppx_ip2_s cn68xxp1;
+};
+
+union cvmx_ciu2_ack_ppx_ip3 {
+       uint64_t u64;
+       struct cvmx_ciu2_ack_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t ack:1;
+#else
+               uint64_t ack:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } s;
+       struct cvmx_ciu2_ack_ppx_ip3_s cn68xx;
+       struct cvmx_ciu2_ack_ppx_ip3_s cn68xxp1;
+};
+
+union cvmx_ciu2_ack_ppx_ip4 {
+       uint64_t u64;
+       struct cvmx_ciu2_ack_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t ack:1;
+#else
+               uint64_t ack:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } s;
+       struct cvmx_ciu2_ack_ppx_ip4_s cn68xx;
+       struct cvmx_ciu2_ack_ppx_ip4_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_gpio_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_gpio_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_gpio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_gpio_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_gpio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_io {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_io_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_io_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_io_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_io_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_io_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_mbox {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_mbox_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_mbox_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_mbox_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_mbox_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_mbox_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_mbox_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_mem_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_mem_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_mem_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_mem_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_mem_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_mio_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_mio_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_mio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_mio_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_mio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_pkt_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_pkt_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_pkt_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_pkt_w1c_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_pkt_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_pkt_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_pkt_w1s_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_rml_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_rml_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_rml_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_rml_w1c_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_rml_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_rml_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_rml_w1s_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_wdog_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_wdog_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_wdog_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_wdog_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_wdog_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_wrkq_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_wrkq_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_wrkq_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_iox_int_wrkq_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_iox_int_wrkq_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xx;
+       struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_gpio_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_gpio_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_io {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_io_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_io_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_io_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_io_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_io_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_mbox {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_mbox_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_mbox_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_mem_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_mem_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_mio_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_mio_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_pkt_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_pkt_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_pkt_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_rml_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_rml_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_rml_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_wdog_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_wdog_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_wrkq_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip2_wrkq_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_gpio_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_gpio_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_io {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_io_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_io_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_io_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_io_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_io_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_mbox {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_mbox_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_mbox_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_mem_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_mem_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_mio_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_mio_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_pkt_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_pkt_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_pkt_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_rml_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_rml_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_rml_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_wdog_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_wdog_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_wrkq_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip3_wrkq_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_gpio_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_gpio_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_io {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_io_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_io_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_io_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_io_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_io_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_mbox {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_mbox_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_mbox_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_mem_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_mem_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_mio_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_mio_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_pkt_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_pkt_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_pkt_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_rml_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_rml_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_rml_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_wdog_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_wdog_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_wrkq_w1c {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xxp1;
+};
+
+union cvmx_ciu2_en_ppx_ip4_wrkq_w1s {
+       uint64_t u64;
+       struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xx;
+       struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xxp1;
+};
+
+union cvmx_ciu2_intr_ciu_ready {
+       uint64_t u64;
+       struct cvmx_ciu2_intr_ciu_ready_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t ready:1;
+#else
+               uint64_t ready:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } s;
+       struct cvmx_ciu2_intr_ciu_ready_s cn68xx;
+       struct cvmx_ciu2_intr_ciu_ready_s cn68xxp1;
+};
+
+union cvmx_ciu2_intr_ram_ecc_ctl {
+       uint64_t u64;
+       struct cvmx_ciu2_intr_ram_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_3_63:61;
+               uint64_t flip_synd:2;
+               uint64_t ecc_ena:1;
+#else
+               uint64_t ecc_ena:1;
+               uint64_t flip_synd:2;
+               uint64_t reserved_3_63:61;
+#endif
+       } s;
+       struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xx;
+       struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xxp1;
+};
+
+union cvmx_ciu2_intr_ram_ecc_st {
+       uint64_t u64;
+       struct cvmx_ciu2_intr_ram_ecc_st_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_23_63:41;
+               uint64_t addr:7;
+               uint64_t reserved_13_15:3;
+               uint64_t syndrom:9;
+               uint64_t reserved_2_3:2;
+               uint64_t dbe:1;
+               uint64_t sbe:1;
+#else
+               uint64_t sbe:1;
+               uint64_t dbe:1;
+               uint64_t reserved_2_3:2;
+               uint64_t syndrom:9;
+               uint64_t reserved_13_15:3;
+               uint64_t addr:7;
+               uint64_t reserved_23_63:41;
+#endif
+       } s;
+       struct cvmx_ciu2_intr_ram_ecc_st_s cn68xx;
+       struct cvmx_ciu2_intr_ram_ecc_st_s cn68xxp1;
+};
+
+union cvmx_ciu2_intr_slowdown {
+       uint64_t u64;
+       struct cvmx_ciu2_intr_slowdown_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_3_63:61;
+               uint64_t ctl:3;
+#else
+               uint64_t ctl:3;
+               uint64_t reserved_3_63:61;
+#endif
+       } s;
+       struct cvmx_ciu2_intr_slowdown_s cn68xx;
+       struct cvmx_ciu2_intr_slowdown_s cn68xxp1;
+};
+
+union cvmx_ciu2_msi_rcvx {
+       uint64_t u64;
+       struct cvmx_ciu2_msi_rcvx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_1_63:63;
+               uint64_t msi_rcv:1;
+#else
+               uint64_t msi_rcv:1;
+               uint64_t reserved_1_63:63;
+#endif
+       } s;
+       struct cvmx_ciu2_msi_rcvx_s cn68xx;
+       struct cvmx_ciu2_msi_rcvx_s cn68xxp1;
+};
+
+union cvmx_ciu2_msi_selx {
+       uint64_t u64;
+       struct cvmx_ciu2_msi_selx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_13_63:51;
+               uint64_t pp_num:5;
+               uint64_t reserved_6_7:2;
+               uint64_t ip_num:2;
+               uint64_t reserved_1_3:3;
+               uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t reserved_1_3:3;
+               uint64_t ip_num:2;
+               uint64_t reserved_6_7:2;
+               uint64_t pp_num:5;
+               uint64_t reserved_13_63:51;
+#endif
+       } s;
+       struct cvmx_ciu2_msi_selx_s cn68xx;
+       struct cvmx_ciu2_msi_selx_s cn68xxp1;
+};
+
+union cvmx_ciu2_msired_ppx_ip2 {
+       uint64_t u64;
+       struct cvmx_ciu2_msired_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_21_63:43;
+               uint64_t intr:1;
+               uint64_t reserved_17_19:3;
+               uint64_t newint:1;
+               uint64_t reserved_8_15:8;
+               uint64_t msi_num:8;
+#else
+               uint64_t msi_num:8;
+               uint64_t reserved_8_15:8;
+               uint64_t newint:1;
+               uint64_t reserved_17_19:3;
+               uint64_t intr:1;
+               uint64_t reserved_21_63:43;
+#endif
+       } s;
+       struct cvmx_ciu2_msired_ppx_ip2_s cn68xx;
+       struct cvmx_ciu2_msired_ppx_ip2_s cn68xxp1;
+};
+
+union cvmx_ciu2_msired_ppx_ip3 {
+       uint64_t u64;
+       struct cvmx_ciu2_msired_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_21_63:43;
+               uint64_t intr:1;
+               uint64_t reserved_17_19:3;
+               uint64_t newint:1;
+               uint64_t reserved_8_15:8;
+               uint64_t msi_num:8;
+#else
+               uint64_t msi_num:8;
+               uint64_t reserved_8_15:8;
+               uint64_t newint:1;
+               uint64_t reserved_17_19:3;
+               uint64_t intr:1;
+               uint64_t reserved_21_63:43;
+#endif
+       } s;
+       struct cvmx_ciu2_msired_ppx_ip3_s cn68xx;
+       struct cvmx_ciu2_msired_ppx_ip3_s cn68xxp1;
+};
+
+union cvmx_ciu2_msired_ppx_ip4 {
+       uint64_t u64;
+       struct cvmx_ciu2_msired_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_21_63:43;
+               uint64_t intr:1;
+               uint64_t reserved_17_19:3;
+               uint64_t newint:1;
+               uint64_t reserved_8_15:8;
+               uint64_t msi_num:8;
+#else
+               uint64_t msi_num:8;
+               uint64_t reserved_8_15:8;
+               uint64_t newint:1;
+               uint64_t reserved_17_19:3;
+               uint64_t intr:1;
+               uint64_t reserved_21_63:43;
+#endif
+       } s;
+       struct cvmx_ciu2_msired_ppx_ip4_s cn68xx;
+       struct cvmx_ciu2_msired_ppx_ip4_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_iox_int_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_iox_int_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_iox_int_gpio_s cn68xx;
+       struct cvmx_ciu2_raw_iox_int_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_iox_int_io {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_iox_int_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_iox_int_io_s cn68xx;
+       struct cvmx_ciu2_raw_iox_int_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_iox_int_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_iox_int_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_iox_int_mem_s cn68xx;
+       struct cvmx_ciu2_raw_iox_int_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_iox_int_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_iox_int_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_iox_int_mio_s cn68xx;
+       struct cvmx_ciu2_raw_iox_int_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_iox_int_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_iox_int_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_iox_int_pkt_s cn68xx;
+       struct cvmx_ciu2_raw_iox_int_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_raw_iox_int_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_iox_int_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_iox_int_rml_s cn68xx;
+       struct cvmx_ciu2_raw_iox_int_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_raw_iox_int_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_iox_int_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_iox_int_wdog_s cn68xx;
+       struct cvmx_ciu2_raw_iox_int_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_iox_int_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_iox_int_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xx;
+       struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip2_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip2_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip2_io {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip2_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip2_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip2_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip2_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip2_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip2_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip2_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip2_pkt_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip2_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip2_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip2_rml_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip2_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip2_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip2_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip2_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip3_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip3_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip3_io {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip3_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip3_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip3_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip3_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip3_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip3_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip3_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip3_pkt_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip3_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip3_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip3_rml_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip3_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip3_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip3_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip3_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip4_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip4_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip4_io {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip4_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip4_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip4_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip4_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip4_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip4_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip4_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip4_pkt_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip4_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip4_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip4_rml_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip4_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip4_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_raw_ppx_ip4_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_raw_ppx_ip4_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xx;
+       struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_iox_int_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_src_iox_int_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_src_iox_int_gpio_s cn68xx;
+       struct cvmx_ciu2_src_iox_int_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_iox_int_io {
+       uint64_t u64;
+       struct cvmx_ciu2_src_iox_int_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_src_iox_int_io_s cn68xx;
+       struct cvmx_ciu2_src_iox_int_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_iox_int_mbox {
+       uint64_t u64;
+       struct cvmx_ciu2_src_iox_int_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_src_iox_int_mbox_s cn68xx;
+       struct cvmx_ciu2_src_iox_int_mbox_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_iox_int_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_src_iox_int_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_src_iox_int_mem_s cn68xx;
+       struct cvmx_ciu2_src_iox_int_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_iox_int_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_src_iox_int_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_src_iox_int_mio_s cn68xx;
+       struct cvmx_ciu2_src_iox_int_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_iox_int_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_src_iox_int_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_src_iox_int_pkt_s cn68xx;
+       struct cvmx_ciu2_src_iox_int_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_src_iox_int_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_src_iox_int_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_src_iox_int_rml_s cn68xx;
+       struct cvmx_ciu2_src_iox_int_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_src_iox_int_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_src_iox_int_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_src_iox_int_wdog_s cn68xx;
+       struct cvmx_ciu2_src_iox_int_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_iox_int_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_src_iox_int_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_src_iox_int_wrkq_s cn68xx;
+       struct cvmx_ciu2_src_iox_int_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip2_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip2_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip2_io {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip2_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip2_io_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip2_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip2_mbox {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip2_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip2_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip2_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip2_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip2_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip2_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip2_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip2_pkt_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip2_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip2_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip2_rml_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip2_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip2_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip2_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip2_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip3_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip3_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip3_io {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip3_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip3_io_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip3_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip3_mbox {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip3_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip3_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip3_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip3_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip3_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip3_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip3_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip3_pkt_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip3_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip3_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip3_rml_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip3_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip3_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip3_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip3_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip4_gpio {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip4_gpio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t gpio:16;
+#else
+               uint64_t gpio:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip4_io {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip4_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_34_63:30;
+               uint64_t pem:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pci_inta:2;
+               uint64_t reserved_13_15:3;
+               uint64_t msired:1;
+               uint64_t pci_msi:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_intr:4;
+#else
+               uint64_t pci_intr:4;
+               uint64_t reserved_4_7:4;
+               uint64_t pci_msi:4;
+               uint64_t msired:1;
+               uint64_t reserved_13_15:3;
+               uint64_t pci_inta:2;
+               uint64_t reserved_18_31:14;
+               uint64_t pem:2;
+               uint64_t reserved_34_63:30;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip4_io_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip4_io_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip4_mbox {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip4_mbox_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t mbox:4;
+#else
+               uint64_t mbox:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip4_mem {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip4_mem_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_4_63:60;
+               uint64_t lmc:4;
+#else
+               uint64_t lmc:4;
+               uint64_t reserved_4_63:60;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip4_mio {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip4_mio_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t rst:1;
+               uint64_t reserved_49_62:14;
+               uint64_t ptp:1;
+               uint64_t reserved_45_47:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_38_39:2;
+               uint64_t uart:2;
+               uint64_t reserved_34_35:2;
+               uint64_t twsi:2;
+               uint64_t reserved_19_31:13;
+               uint64_t bootdma:1;
+               uint64_t mio:1;
+               uint64_t nand:1;
+               uint64_t reserved_12_15:4;
+               uint64_t timer:4;
+               uint64_t reserved_3_7:5;
+               uint64_t ipd_drp:1;
+               uint64_t ssoiq:1;
+               uint64_t ipdppthr:1;
+#else
+               uint64_t ipdppthr:1;
+               uint64_t ssoiq:1;
+               uint64_t ipd_drp:1;
+               uint64_t reserved_3_7:5;
+               uint64_t timer:4;
+               uint64_t reserved_12_15:4;
+               uint64_t nand:1;
+               uint64_t mio:1;
+               uint64_t bootdma:1;
+               uint64_t reserved_19_31:13;
+               uint64_t twsi:2;
+               uint64_t reserved_34_35:2;
+               uint64_t uart:2;
+               uint64_t reserved_38_39:2;
+               uint64_t usb_uctl:1;
+               uint64_t reserved_41_43:3;
+               uint64_t usb_hci:1;
+               uint64_t reserved_45_47:3;
+               uint64_t ptp:1;
+               uint64_t reserved_49_62:14;
+               uint64_t rst:1;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip4_pkt {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip4_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_54_63:10;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_51:3;
+               uint64_t ilk_drp:2;
+               uint64_t reserved_54_63:10;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip4_pkt_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_49_63:15;
+               uint64_t ilk:1;
+               uint64_t reserved_41_47:7;
+               uint64_t mii:1;
+               uint64_t reserved_33_39:7;
+               uint64_t agl:1;
+               uint64_t reserved_13_31:19;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_5_7:3;
+               uint64_t agx:5;
+#else
+               uint64_t agx:5;
+               uint64_t reserved_5_7:3;
+               uint64_t gmx_drp:5;
+               uint64_t reserved_13_31:19;
+               uint64_t agl:1;
+               uint64_t reserved_33_39:7;
+               uint64_t mii:1;
+               uint64_t reserved_41_47:7;
+               uint64_t ilk:1;
+               uint64_t reserved_49_63:15;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip4_rml {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip4_rml_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_35:2;
+               uint64_t dpi_dma:1;
+               uint64_t reserved_37_39:3;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip4_rml_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_56_63:8;
+               uint64_t trace:4;
+               uint64_t reserved_49_51:3;
+               uint64_t l2c:1;
+               uint64_t reserved_41_47:7;
+               uint64_t dfa:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dpi:1;
+               uint64_t sli:1;
+               uint64_t reserved_31_31:1;
+               uint64_t key:1;
+               uint64_t rad:1;
+               uint64_t tim:1;
+               uint64_t reserved_25_27:3;
+               uint64_t zip:1;
+               uint64_t reserved_17_23:7;
+               uint64_t sso:1;
+               uint64_t reserved_8_15:8;
+               uint64_t pko:1;
+               uint64_t pip:1;
+               uint64_t ipd:1;
+               uint64_t fpa:1;
+               uint64_t reserved_1_3:3;
+               uint64_t iob:1;
+#else
+               uint64_t iob:1;
+               uint64_t reserved_1_3:3;
+               uint64_t fpa:1;
+               uint64_t ipd:1;
+               uint64_t pip:1;
+               uint64_t pko:1;
+               uint64_t reserved_8_15:8;
+               uint64_t sso:1;
+               uint64_t reserved_17_23:7;
+               uint64_t zip:1;
+               uint64_t reserved_25_27:3;
+               uint64_t tim:1;
+               uint64_t rad:1;
+               uint64_t key:1;
+               uint64_t reserved_31_31:1;
+               uint64_t sli:1;
+               uint64_t dpi:1;
+               uint64_t reserved_34_39:6;
+               uint64_t dfa:1;
+               uint64_t reserved_41_47:7;
+               uint64_t l2c:1;
+               uint64_t reserved_49_51:3;
+               uint64_t trace:4;
+               uint64_t reserved_56_63:8;
+#endif
+       } cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip4_wdog {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip4_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t wdog:32;
+#else
+               uint64_t wdog:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xxp1;
+};
+
+union cvmx_ciu2_src_ppx_ip4_wrkq {
+       uint64_t u64;
+       struct cvmx_ciu2_src_ppx_ip4_wrkq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t workq:64;
+#else
+               uint64_t workq:64;
+#endif
+       } s;
+       struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xx;
+       struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xxp1;
+};
+
+union cvmx_ciu2_sum_iox_int {
+       uint64_t u64;
+       struct cvmx_ciu2_sum_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t mbox:4;
+               uint64_t reserved_8_59:52;
+               uint64_t gpio:1;
+               uint64_t pkt:1;
+               uint64_t mem:1;
+               uint64_t io:1;
+               uint64_t mio:1;
+               uint64_t rml:1;
+               uint64_t wdog:1;
+               uint64_t workq:1;
+#else
+               uint64_t workq:1;
+               uint64_t wdog:1;
+               uint64_t rml:1;
+               uint64_t mio:1;
+               uint64_t io:1;
+               uint64_t mem:1;
+               uint64_t pkt:1;
+               uint64_t gpio:1;
+               uint64_t reserved_8_59:52;
+               uint64_t mbox:4;
+#endif
+       } s;
+       struct cvmx_ciu2_sum_iox_int_s cn68xx;
+       struct cvmx_ciu2_sum_iox_int_s cn68xxp1;
+};
+
+union cvmx_ciu2_sum_ppx_ip2 {
+       uint64_t u64;
+       struct cvmx_ciu2_sum_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t mbox:4;
+               uint64_t reserved_8_59:52;
+               uint64_t gpio:1;
+               uint64_t pkt:1;
+               uint64_t mem:1;
+               uint64_t io:1;
+               uint64_t mio:1;
+               uint64_t rml:1;
+               uint64_t wdog:1;
+               uint64_t workq:1;
+#else
+               uint64_t workq:1;
+               uint64_t wdog:1;
+               uint64_t rml:1;
+               uint64_t mio:1;
+               uint64_t io:1;
+               uint64_t mem:1;
+               uint64_t pkt:1;
+               uint64_t gpio:1;
+               uint64_t reserved_8_59:52;
+               uint64_t mbox:4;
+#endif
+       } s;
+       struct cvmx_ciu2_sum_ppx_ip2_s cn68xx;
+       struct cvmx_ciu2_sum_ppx_ip2_s cn68xxp1;
+};
+
+union cvmx_ciu2_sum_ppx_ip3 {
+       uint64_t u64;
+       struct cvmx_ciu2_sum_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t mbox:4;
+               uint64_t reserved_8_59:52;
+               uint64_t gpio:1;
+               uint64_t pkt:1;
+               uint64_t mem:1;
+               uint64_t io:1;
+               uint64_t mio:1;
+               uint64_t rml:1;
+               uint64_t wdog:1;
+               uint64_t workq:1;
+#else
+               uint64_t workq:1;
+               uint64_t wdog:1;
+               uint64_t rml:1;
+               uint64_t mio:1;
+               uint64_t io:1;
+               uint64_t mem:1;
+               uint64_t pkt:1;
+               uint64_t gpio:1;
+               uint64_t reserved_8_59:52;
+               uint64_t mbox:4;
+#endif
+       } s;
+       struct cvmx_ciu2_sum_ppx_ip3_s cn68xx;
+       struct cvmx_ciu2_sum_ppx_ip3_s cn68xxp1;
+};
+
+union cvmx_ciu2_sum_ppx_ip4 {
+       uint64_t u64;
+       struct cvmx_ciu2_sum_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t mbox:4;
+               uint64_t reserved_8_59:52;
+               uint64_t gpio:1;
+               uint64_t pkt:1;
+               uint64_t mem:1;
+               uint64_t io:1;
+               uint64_t mio:1;
+               uint64_t rml:1;
+               uint64_t wdog:1;
+               uint64_t workq:1;
+#else
+               uint64_t workq:1;
+               uint64_t wdog:1;
+               uint64_t rml:1;
+               uint64_t mio:1;
+               uint64_t io:1;
+               uint64_t mem:1;
+               uint64_t pkt:1;
+               uint64_t gpio:1;
+               uint64_t reserved_8_59:52;
+               uint64_t mbox:4;
+#endif
+       } s;
+       struct cvmx_ciu2_sum_ppx_ip4_s cn68xx;
+       struct cvmx_ciu2_sum_ppx_ip4_s cn68xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h 
b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
index abbf42d..40799cd 100644
--- a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,27 +28,43 @@
 #ifndef __CVMX_DBG_DEFS_H__
 #define __CVMX_DBG_DEFS_H__
 
-#define CVMX_DBG_DATA \
-        CVMX_ADD_IO_SEG(0x00011F00000001E8ull)
+#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
 
 union cvmx_dbg_data {
        uint64_t u64;
        struct cvmx_dbg_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_23_63:41;
                uint64_t c_mul:5;
                uint64_t dsel_ext:1;
                uint64_t data:17;
+#else
+               uint64_t data:17;
+               uint64_t dsel_ext:1;
+               uint64_t c_mul:5;
+               uint64_t reserved_23_63:41;
+#endif
        } s;
        struct cvmx_dbg_data_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_31_63:33;
                uint64_t pll_mul:3;
                uint64_t reserved_23_27:5;
                uint64_t c_mul:5;
                uint64_t dsel_ext:1;
                uint64_t data:17;
+#else
+               uint64_t data:17;
+               uint64_t dsel_ext:1;
+               uint64_t c_mul:5;
+               uint64_t reserved_23_27:5;
+               uint64_t pll_mul:3;
+               uint64_t reserved_31_63:33;
+#endif
        } cn30xx;
        struct cvmx_dbg_data_cn30xx cn31xx;
        struct cvmx_dbg_data_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_29_63:35;
                uint64_t d_mul:4;
                uint64_t dclk_mul2:1;
@@ -56,15 +72,32 @@ union cvmx_dbg_data {
                uint64_t c_mul:5;
                uint64_t dsel_ext:1;
                uint64_t data:17;
+#else
+               uint64_t data:17;
+               uint64_t dsel_ext:1;
+               uint64_t c_mul:5;
+               uint64_t cclk_div2:1;
+               uint64_t dclk_mul2:1;
+               uint64_t d_mul:4;
+               uint64_t reserved_29_63:35;
+#endif
        } cn38xx;
        struct cvmx_dbg_data_cn38xx cn38xxp2;
        struct cvmx_dbg_data_cn30xx cn50xx;
        struct cvmx_dbg_data_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_29_63:35;
                uint64_t rem:6;
                uint64_t c_mul:5;
                uint64_t dsel_ext:1;
                uint64_t data:17;
+#else
+               uint64_t data:17;
+               uint64_t dsel_ext:1;
+               uint64_t c_mul:5;
+               uint64_t rem:6;
+               uint64_t reserved_29_63:35;
+#endif
        } cn58xx;
        struct cvmx_dbg_data_cn58xx cn58xxp1;
 };
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h 
b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
index c34ad04..dd5b042 100644
--- a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2011 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -55,52 +55,107 @@
 #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
 #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
 #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) 
+ ((offset) & 3) * 8)
+static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+
+               if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
+                       return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + 
(offset) * 8;
+
+               if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
+                       return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + 
(offset) * 8;
+               return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
+       }
+       return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+}
+
 #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) 
(CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
 
 union cvmx_dpi_bist_status {
        uint64_t u64;
        struct cvmx_dpi_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_47_63:17;
                uint64_t bist:47;
+#else
+               uint64_t bist:47;
+               uint64_t reserved_47_63:17;
+#endif
        } s;
        struct cvmx_dpi_bist_status_s cn61xx;
        struct cvmx_dpi_bist_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_45_63:19;
                uint64_t bist:45;
+#else
+               uint64_t bist:45;
+               uint64_t reserved_45_63:19;
+#endif
        } cn63xx;
        struct cvmx_dpi_bist_status_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_37_63:27;
                uint64_t bist:37;
+#else
+               uint64_t bist:37;
+               uint64_t reserved_37_63:27;
+#endif
        } cn63xxp1;
        struct cvmx_dpi_bist_status_s cn66xx;
        struct cvmx_dpi_bist_status_cn63xx cn68xx;
        struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
+       struct cvmx_dpi_bist_status_s cnf71xx;
 };
 
 union cvmx_dpi_ctl {
        uint64_t u64;
        struct cvmx_dpi_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_2_63:62;
                uint64_t clk:1;
                uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t clk:1;
+               uint64_t reserved_2_63:62;
+#endif
        } s;
        struct cvmx_dpi_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t reserved_1_63:63;
+#endif
        } cn61xx;
        struct cvmx_dpi_ctl_s cn63xx;
        struct cvmx_dpi_ctl_s cn63xxp1;
        struct cvmx_dpi_ctl_s cn66xx;
        struct cvmx_dpi_ctl_s cn68xx;
        struct cvmx_dpi_ctl_s cn68xxp1;
+       struct cvmx_dpi_ctl_cn61xx cnf71xx;
 };
 
 union cvmx_dpi_dmax_counts {
        uint64_t u64;
        struct cvmx_dpi_dmax_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_39_63:25;
                uint64_t fcnt:7;
                uint64_t dbell:32;
+#else
+               uint64_t dbell:32;
+               uint64_t fcnt:7;
+               uint64_t reserved_39_63:25;
+#endif
        } s;
        struct cvmx_dpi_dmax_counts_s cn61xx;
        struct cvmx_dpi_dmax_counts_s cn63xx;
@@ -108,13 +163,19 @@ union cvmx_dpi_dmax_counts {
        struct cvmx_dpi_dmax_counts_s cn66xx;
        struct cvmx_dpi_dmax_counts_s cn68xx;
        struct cvmx_dpi_dmax_counts_s cn68xxp1;
+       struct cvmx_dpi_dmax_counts_s cnf71xx;
 };
 
 union cvmx_dpi_dmax_dbell {
        uint64_t u64;
        struct cvmx_dpi_dmax_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t dbell:16;
+#else
+               uint64_t dbell:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_dpi_dmax_dbell_s cn61xx;
        struct cvmx_dpi_dmax_dbell_s cn63xx;
@@ -122,31 +183,48 @@ union cvmx_dpi_dmax_dbell {
        struct cvmx_dpi_dmax_dbell_s cn66xx;
        struct cvmx_dpi_dmax_dbell_s cn68xx;
        struct cvmx_dpi_dmax_dbell_s cn68xxp1;
+       struct cvmx_dpi_dmax_dbell_s cnf71xx;
 };
 
 union cvmx_dpi_dmax_err_rsp_status {
        uint64_t u64;
        struct cvmx_dpi_dmax_err_rsp_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t status:6;
+#else
+               uint64_t status:6;
+               uint64_t reserved_6_63:58;
+#endif
        } s;
        struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
        struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
        struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
        struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
+       struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;
 };
 
 union cvmx_dpi_dmax_ibuff_saddr {
        uint64_t u64;
        struct cvmx_dpi_dmax_ibuff_saddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_62_63:2;
                uint64_t csize:14;
                uint64_t reserved_41_47:7;
                uint64_t idle:1;
                uint64_t saddr:33;
                uint64_t reserved_0_6:7;
+#else
+               uint64_t reserved_0_6:7;
+               uint64_t saddr:33;
+               uint64_t idle:1;
+               uint64_t reserved_41_47:7;
+               uint64_t csize:14;
+               uint64_t reserved_62_63:2;
+#endif
        } s;
        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_62_63:2;
                uint64_t csize:14;
                uint64_t reserved_41_47:7;
@@ -154,47 +232,78 @@ union cvmx_dpi_dmax_ibuff_saddr {
                uint64_t reserved_36_39:4;
                uint64_t saddr:29;
                uint64_t reserved_0_6:7;
+#else
+               uint64_t reserved_0_6:7;
+               uint64_t saddr:29;
+               uint64_t reserved_36_39:4;
+               uint64_t idle:1;
+               uint64_t reserved_41_47:7;
+               uint64_t csize:14;
+               uint64_t reserved_62_63:2;
+#endif
        } cn61xx;
        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
        struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
        struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
+       struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;
 };
 
 union cvmx_dpi_dmax_iflight {
        uint64_t u64;
        struct cvmx_dpi_dmax_iflight_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_3_63:61;
                uint64_t cnt:3;
+#else
+               uint64_t cnt:3;
+               uint64_t reserved_3_63:61;
+#endif
        } s;
        struct cvmx_dpi_dmax_iflight_s cn61xx;
        struct cvmx_dpi_dmax_iflight_s cn66xx;
        struct cvmx_dpi_dmax_iflight_s cn68xx;
        struct cvmx_dpi_dmax_iflight_s cn68xxp1;
+       struct cvmx_dpi_dmax_iflight_s cnf71xx;
 };
 
 union cvmx_dpi_dmax_naddr {
        uint64_t u64;
        struct cvmx_dpi_dmax_naddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_40_63:24;
                uint64_t addr:40;
+#else
+               uint64_t addr:40;
+               uint64_t reserved_40_63:24;
+#endif
        } s;
        struct cvmx_dpi_dmax_naddr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_36_63:28;
                uint64_t addr:36;
+#else
+               uint64_t addr:36;
+               uint64_t reserved_36_63:28;
+#endif
        } cn61xx;
        struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
        struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
        struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
        struct cvmx_dpi_dmax_naddr_s cn68xx;
        struct cvmx_dpi_dmax_naddr_s cn68xxp1;
+       struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx;
 };
 
 union cvmx_dpi_dmax_reqbnk0 {
        uint64_t u64;
        struct cvmx_dpi_dmax_reqbnk0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t state:64;
+#else
+               uint64_t state:64;
+#endif
        } s;
        struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
        struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
@@ -202,12 +311,17 @@ union cvmx_dpi_dmax_reqbnk0 {
        struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
        struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
        struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
+       struct cvmx_dpi_dmax_reqbnk0_s cnf71xx;
 };
 
 union cvmx_dpi_dmax_reqbnk1 {
        uint64_t u64;
        struct cvmx_dpi_dmax_reqbnk1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t state:64;
+#else
                uint64_t state:64;
+#endif
        } s;
        struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
        struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
@@ -215,11 +329,13 @@ union cvmx_dpi_dmax_reqbnk1 {
        struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
        struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
        struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
+       struct cvmx_dpi_dmax_reqbnk1_s cnf71xx;
 };
 
 union cvmx_dpi_dma_control {
        uint64_t u64;
        struct cvmx_dpi_dma_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_62_63:2;
                uint64_t dici_mode:1;
                uint64_t pkt_en1:1;
@@ -240,9 +356,32 @@ union cvmx_dpi_dma_control {
                uint64_t o_es:2;
                uint64_t o_mode:1;
                uint64_t reserved_0_13:14;
+#else
+               uint64_t reserved_0_13:14;
+               uint64_t o_mode:1;
+               uint64_t o_es:2;
+               uint64_t o_ns:1;
+               uint64_t o_ro:1;
+               uint64_t o_add1:1;
+               uint64_t fpa_que:3;
+               uint64_t dwb_ichk:9;
+               uint64_t dwb_denb:1;
+               uint64_t b0_lend:1;
+               uint64_t reserved_34_47:14;
+               uint64_t dma_enb:6;
+               uint64_t reserved_54_55:2;
+               uint64_t pkt_en:1;
+               uint64_t pkt_hp:1;
+               uint64_t commit_mode:1;
+               uint64_t ffp_dis:1;
+               uint64_t pkt_en1:1;
+               uint64_t dici_mode:1;
+               uint64_t reserved_62_63:2;
+#endif
        } s;
        struct cvmx_dpi_dma_control_s cn61xx;
        struct cvmx_dpi_dma_control_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_61_63:3;
                uint64_t pkt_en1:1;
                uint64_t ffp_dis:1;
@@ -262,8 +401,30 @@ union cvmx_dpi_dma_control {
                uint64_t o_es:2;
                uint64_t o_mode:1;
                uint64_t reserved_0_13:14;
+#else
+               uint64_t reserved_0_13:14;
+               uint64_t o_mode:1;
+               uint64_t o_es:2;
+               uint64_t o_ns:1;
+               uint64_t o_ro:1;
+               uint64_t o_add1:1;
+               uint64_t fpa_que:3;
+               uint64_t dwb_ichk:9;
+               uint64_t dwb_denb:1;
+               uint64_t b0_lend:1;
+               uint64_t reserved_34_47:14;
+               uint64_t dma_enb:6;
+               uint64_t reserved_54_55:2;
+               uint64_t pkt_en:1;
+               uint64_t pkt_hp:1;
+               uint64_t commit_mode:1;
+               uint64_t ffp_dis:1;
+               uint64_t pkt_en1:1;
+               uint64_t reserved_61_63:3;
+#endif
        } cn63xx;
        struct cvmx_dpi_dma_control_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_59_63:5;
                uint64_t commit_mode:1;
                uint64_t pkt_hp:1;
@@ -281,17 +442,42 @@ union cvmx_dpi_dma_control {
                uint64_t o_es:2;
                uint64_t o_mode:1;
                uint64_t reserved_0_13:14;
+#else
+               uint64_t reserved_0_13:14;
+               uint64_t o_mode:1;
+               uint64_t o_es:2;
+               uint64_t o_ns:1;
+               uint64_t o_ro:1;
+               uint64_t o_add1:1;
+               uint64_t fpa_que:3;
+               uint64_t dwb_ichk:9;
+               uint64_t dwb_denb:1;
+               uint64_t b0_lend:1;
+               uint64_t reserved_34_47:14;
+               uint64_t dma_enb:6;
+               uint64_t reserved_54_55:2;
+               uint64_t pkt_en:1;
+               uint64_t pkt_hp:1;
+               uint64_t commit_mode:1;
+               uint64_t reserved_59_63:5;
+#endif
        } cn63xxp1;
        struct cvmx_dpi_dma_control_cn63xx cn66xx;
        struct cvmx_dpi_dma_control_s cn68xx;
        struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
+       struct cvmx_dpi_dma_control_s cnf71xx;
 };
 
 union cvmx_dpi_dma_engx_en {
        uint64_t u64;
        struct cvmx_dpi_dma_engx_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t qen:8;
+#else
+               uint64_t qen:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_dpi_dma_engx_en_s cn61xx;
        struct cvmx_dpi_dma_engx_en_s cn63xx;
@@ -299,63 +485,101 @@ union cvmx_dpi_dma_engx_en {
        struct cvmx_dpi_dma_engx_en_s cn66xx;
        struct cvmx_dpi_dma_engx_en_s cn68xx;
        struct cvmx_dpi_dma_engx_en_s cn68xxp1;
+       struct cvmx_dpi_dma_engx_en_s cnf71xx;
 };
 
 union cvmx_dpi_dma_ppx_cnt {
        uint64_t u64;
        struct cvmx_dpi_dma_ppx_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t cnt:16;
+#else
+               uint64_t cnt:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
        struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
+       struct cvmx_dpi_dma_ppx_cnt_s cnf71xx;
 };
 
 union cvmx_dpi_engx_buf {
        uint64_t u64;
        struct cvmx_dpi_engx_buf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_37_63:27;
                uint64_t compblks:5;
                uint64_t reserved_9_31:23;
                uint64_t base:5;
                uint64_t blks:4;
+#else
+               uint64_t blks:4;
+               uint64_t base:5;
+               uint64_t reserved_9_31:23;
+               uint64_t compblks:5;
+               uint64_t reserved_37_63:27;
+#endif
        } s;
        struct cvmx_dpi_engx_buf_s cn61xx;
        struct cvmx_dpi_engx_buf_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t base:4;
                uint64_t blks:4;
+#else
+               uint64_t blks:4;
+               uint64_t base:4;
+               uint64_t reserved_8_63:56;
+#endif
        } cn63xx;
        struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
        struct cvmx_dpi_engx_buf_s cn66xx;
        struct cvmx_dpi_engx_buf_s cn68xx;
        struct cvmx_dpi_engx_buf_s cn68xxp1;
+       struct cvmx_dpi_engx_buf_s cnf71xx;
 };
 
 union cvmx_dpi_info_reg {
        uint64_t u64;
        struct cvmx_dpi_info_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t ffp:4;
                uint64_t reserved_2_3:2;
                uint64_t ncb:1;
                uint64_t rsl:1;
+#else
+               uint64_t rsl:1;
+               uint64_t ncb:1;
+               uint64_t reserved_2_3:2;
+               uint64_t ffp:4;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_dpi_info_reg_s cn61xx;
        struct cvmx_dpi_info_reg_s cn63xx;
        struct cvmx_dpi_info_reg_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_2_63:62;
                uint64_t ncb:1;
                uint64_t rsl:1;
+#else
+               uint64_t rsl:1;
+               uint64_t ncb:1;
+               uint64_t reserved_2_63:62;
+#endif
        } cn63xxp1;
        struct cvmx_dpi_info_reg_s cn66xx;
        struct cvmx_dpi_info_reg_s cn68xx;
        struct cvmx_dpi_info_reg_s cn68xxp1;
+       struct cvmx_dpi_info_reg_s cnf71xx;
 };
 
 union cvmx_dpi_int_en {
        uint64_t u64;
        struct cvmx_dpi_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_28_63:36;
                uint64_t sprt3_rst:1;
                uint64_t sprt2_rst:1;
@@ -373,9 +597,29 @@ union cvmx_dpi_int_en {
                uint64_t reserved_2_7:6;
                uint64_t nfovr:1;
                uint64_t nderr:1;
+#else
+               uint64_t nderr:1;
+               uint64_t nfovr:1;
+               uint64_t reserved_2_7:6;
+               uint64_t dmadbo:8;
+               uint64_t req_badadr:1;
+               uint64_t req_badlen:1;
+               uint64_t req_ovrflw:1;
+               uint64_t req_undflw:1;
+               uint64_t req_anull:1;
+               uint64_t req_inull:1;
+               uint64_t req_badfil:1;
+               uint64_t reserved_23_23:1;
+               uint64_t sprt0_rst:1;
+               uint64_t sprt1_rst:1;
+               uint64_t sprt2_rst:1;
+               uint64_t sprt3_rst:1;
+               uint64_t reserved_28_63:36;
+#endif
        } s;
        struct cvmx_dpi_int_en_s cn61xx;
        struct cvmx_dpi_int_en_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_26_63:38;
                uint64_t sprt1_rst:1;
                uint64_t sprt0_rst:1;
@@ -391,16 +635,35 @@ union cvmx_dpi_int_en {
                uint64_t reserved_2_7:6;
                uint64_t nfovr:1;
                uint64_t nderr:1;
+#else
+               uint64_t nderr:1;
+               uint64_t nfovr:1;
+               uint64_t reserved_2_7:6;
+               uint64_t dmadbo:8;
+               uint64_t req_badadr:1;
+               uint64_t req_badlen:1;
+               uint64_t req_ovrflw:1;
+               uint64_t req_undflw:1;
+               uint64_t req_anull:1;
+               uint64_t req_inull:1;
+               uint64_t req_badfil:1;
+               uint64_t reserved_23_23:1;
+               uint64_t sprt0_rst:1;
+               uint64_t sprt1_rst:1;
+               uint64_t reserved_26_63:38;
+#endif
        } cn63xx;
        struct cvmx_dpi_int_en_cn63xx cn63xxp1;
        struct cvmx_dpi_int_en_s cn66xx;
        struct cvmx_dpi_int_en_cn63xx cn68xx;
        struct cvmx_dpi_int_en_cn63xx cn68xxp1;
+       struct cvmx_dpi_int_en_s cnf71xx;
 };
 
 union cvmx_dpi_int_reg {
        uint64_t u64;
        struct cvmx_dpi_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_28_63:36;
                uint64_t sprt3_rst:1;
                uint64_t sprt2_rst:1;
@@ -418,9 +681,29 @@ union cvmx_dpi_int_reg {
                uint64_t reserved_2_7:6;
                uint64_t nfovr:1;
                uint64_t nderr:1;
+#else
+               uint64_t nderr:1;
+               uint64_t nfovr:1;
+               uint64_t reserved_2_7:6;
+               uint64_t dmadbo:8;
+               uint64_t req_badadr:1;
+               uint64_t req_badlen:1;
+               uint64_t req_ovrflw:1;
+               uint64_t req_undflw:1;
+               uint64_t req_anull:1;
+               uint64_t req_inull:1;
+               uint64_t req_badfil:1;
+               uint64_t reserved_23_23:1;
+               uint64_t sprt0_rst:1;
+               uint64_t sprt1_rst:1;
+               uint64_t sprt2_rst:1;
+               uint64_t sprt3_rst:1;
+               uint64_t reserved_28_63:36;
+#endif
        } s;
        struct cvmx_dpi_int_reg_s cn61xx;
        struct cvmx_dpi_int_reg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_26_63:38;
                uint64_t sprt1_rst:1;
                uint64_t sprt0_rst:1;
@@ -436,31 +719,62 @@ union cvmx_dpi_int_reg {
                uint64_t reserved_2_7:6;
                uint64_t nfovr:1;
                uint64_t nderr:1;
+#else
+               uint64_t nderr:1;
+               uint64_t nfovr:1;
+               uint64_t reserved_2_7:6;
+               uint64_t dmadbo:8;
+               uint64_t req_badadr:1;
+               uint64_t req_badlen:1;
+               uint64_t req_ovrflw:1;
+               uint64_t req_undflw:1;
+               uint64_t req_anull:1;
+               uint64_t req_inull:1;
+               uint64_t req_badfil:1;
+               uint64_t reserved_23_23:1;
+               uint64_t sprt0_rst:1;
+               uint64_t sprt1_rst:1;
+               uint64_t reserved_26_63:38;
+#endif
        } cn63xx;
        struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
        struct cvmx_dpi_int_reg_s cn66xx;
        struct cvmx_dpi_int_reg_cn63xx cn68xx;
        struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
+       struct cvmx_dpi_int_reg_s cnf71xx;
 };
 
 union cvmx_dpi_ncbx_cfg {
        uint64_t u64;
        struct cvmx_dpi_ncbx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t molr:6;
+#else
+               uint64_t molr:6;
+               uint64_t reserved_6_63:58;
+#endif
        } s;
        struct cvmx_dpi_ncbx_cfg_s cn61xx;
        struct cvmx_dpi_ncbx_cfg_s cn66xx;
        struct cvmx_dpi_ncbx_cfg_s cn68xx;
+       struct cvmx_dpi_ncbx_cfg_s cnf71xx;
 };
 
 union cvmx_dpi_pint_info {
        uint64_t u64;
        struct cvmx_dpi_pint_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_14_63:50;
                uint64_t iinfo:6;
                uint64_t reserved_6_7:2;
                uint64_t sinfo:6;
+#else
+               uint64_t sinfo:6;
+               uint64_t reserved_6_7:2;
+               uint64_t iinfo:6;
+               uint64_t reserved_14_63:50;
+#endif
        } s;
        struct cvmx_dpi_pint_info_s cn61xx;
        struct cvmx_dpi_pint_info_s cn63xx;
@@ -468,13 +782,19 @@ union cvmx_dpi_pint_info {
        struct cvmx_dpi_pint_info_s cn66xx;
        struct cvmx_dpi_pint_info_s cn68xx;
        struct cvmx_dpi_pint_info_s cn68xxp1;
+       struct cvmx_dpi_pint_info_s cnf71xx;
 };
 
 union cvmx_dpi_pkt_err_rsp {
        uint64_t u64;
        struct cvmx_dpi_pkt_err_rsp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t pkterr:1;
+#else
+               uint64_t pkterr:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
        struct cvmx_dpi_pkt_err_rsp_s cn61xx;
        struct cvmx_dpi_pkt_err_rsp_s cn63xx;
@@ -482,13 +802,19 @@ union cvmx_dpi_pkt_err_rsp {
        struct cvmx_dpi_pkt_err_rsp_s cn66xx;
        struct cvmx_dpi_pkt_err_rsp_s cn68xx;
        struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
+       struct cvmx_dpi_pkt_err_rsp_s cnf71xx;
 };
 
 union cvmx_dpi_req_err_rsp {
        uint64_t u64;
        struct cvmx_dpi_req_err_rsp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t qerr:8;
+#else
+               uint64_t qerr:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_dpi_req_err_rsp_s cn61xx;
        struct cvmx_dpi_req_err_rsp_s cn63xx;
@@ -496,13 +822,19 @@ union cvmx_dpi_req_err_rsp {
        struct cvmx_dpi_req_err_rsp_s cn66xx;
        struct cvmx_dpi_req_err_rsp_s cn68xx;
        struct cvmx_dpi_req_err_rsp_s cn68xxp1;
+       struct cvmx_dpi_req_err_rsp_s cnf71xx;
 };
 
 union cvmx_dpi_req_err_rsp_en {
        uint64_t u64;
        struct cvmx_dpi_req_err_rsp_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t en:8;
+#else
+               uint64_t en:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_dpi_req_err_rsp_en_s cn61xx;
        struct cvmx_dpi_req_err_rsp_en_s cn63xx;
@@ -510,13 +842,19 @@ union cvmx_dpi_req_err_rsp_en {
        struct cvmx_dpi_req_err_rsp_en_s cn66xx;
        struct cvmx_dpi_req_err_rsp_en_s cn68xx;
        struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
+       struct cvmx_dpi_req_err_rsp_en_s cnf71xx;
 };
 
 union cvmx_dpi_req_err_rst {
        uint64_t u64;
        struct cvmx_dpi_req_err_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t qerr:8;
+#else
+               uint64_t qerr:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_dpi_req_err_rst_s cn61xx;
        struct cvmx_dpi_req_err_rst_s cn63xx;
@@ -524,13 +862,19 @@ union cvmx_dpi_req_err_rst {
        struct cvmx_dpi_req_err_rst_s cn66xx;
        struct cvmx_dpi_req_err_rst_s cn68xx;
        struct cvmx_dpi_req_err_rst_s cn68xxp1;
+       struct cvmx_dpi_req_err_rst_s cnf71xx;
 };
 
 union cvmx_dpi_req_err_rst_en {
        uint64_t u64;
        struct cvmx_dpi_req_err_rst_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t en:8;
+#else
+               uint64_t en:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_dpi_req_err_rst_en_s cn61xx;
        struct cvmx_dpi_req_err_rst_en_s cn63xx;
@@ -538,27 +882,41 @@ union cvmx_dpi_req_err_rst_en {
        struct cvmx_dpi_req_err_rst_en_s cn66xx;
        struct cvmx_dpi_req_err_rst_en_s cn68xx;
        struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
+       struct cvmx_dpi_req_err_rst_en_s cnf71xx;
 };
 
 union cvmx_dpi_req_err_skip_comp {
        uint64_t u64;
        struct cvmx_dpi_req_err_skip_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_24_63:40;
                uint64_t en_rst:8;
                uint64_t reserved_8_15:8;
                uint64_t en_rsp:8;
+#else
+               uint64_t en_rsp:8;
+               uint64_t reserved_8_15:8;
+               uint64_t en_rst:8;
+               uint64_t reserved_24_63:40;
+#endif
        } s;
        struct cvmx_dpi_req_err_skip_comp_s cn61xx;
        struct cvmx_dpi_req_err_skip_comp_s cn66xx;
        struct cvmx_dpi_req_err_skip_comp_s cn68xx;
        struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
+       struct cvmx_dpi_req_err_skip_comp_s cnf71xx;
 };
 
 union cvmx_dpi_req_gbl_en {
        uint64_t u64;
        struct cvmx_dpi_req_gbl_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t qen:8;
+#else
+               uint64_t qen:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_dpi_req_gbl_en_s cn61xx;
        struct cvmx_dpi_req_gbl_en_s cn63xx;
@@ -566,11 +924,13 @@ union cvmx_dpi_req_gbl_en {
        struct cvmx_dpi_req_gbl_en_s cn66xx;
        struct cvmx_dpi_req_gbl_en_s cn68xx;
        struct cvmx_dpi_req_gbl_en_s cn68xxp1;
+       struct cvmx_dpi_req_gbl_en_s cnf71xx;
 };
 
 union cvmx_dpi_sli_prtx_cfg {
        uint64_t u64;
        struct cvmx_dpi_sli_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_25_63:39;
                uint64_t halt:1;
                uint64_t qlm_cfg:4;
@@ -584,9 +944,25 @@ union cvmx_dpi_sli_prtx_cfg {
                uint64_t mrrs_lim:1;
                uint64_t reserved_2_2:1;
                uint64_t mrrs:2;
+#else
+               uint64_t mrrs:2;
+               uint64_t reserved_2_2:1;
+               uint64_t mrrs_lim:1;
+               uint64_t mps:1;
+               uint64_t reserved_5_6:2;
+               uint64_t mps_lim:1;
+               uint64_t molr:6;
+               uint64_t reserved_14_15:2;
+               uint64_t rd_mode:1;
+               uint64_t reserved_17_19:3;
+               uint64_t qlm_cfg:4;
+               uint64_t halt:1;
+               uint64_t reserved_25_63:39;
+#endif
        } s;
        struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
        struct cvmx_dpi_sli_prtx_cfg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_25_63:39;
                uint64_t halt:1;
                uint64_t reserved_21_23:3;
@@ -601,18 +977,40 @@ union cvmx_dpi_sli_prtx_cfg {
                uint64_t mrrs_lim:1;
                uint64_t reserved_2_2:1;
                uint64_t mrrs:2;
+#else
+               uint64_t mrrs:2;
+               uint64_t reserved_2_2:1;
+               uint64_t mrrs_lim:1;
+               uint64_t mps:1;
+               uint64_t reserved_5_6:2;
+               uint64_t mps_lim:1;
+               uint64_t molr:6;
+               uint64_t reserved_14_15:2;
+               uint64_t rd_mode:1;
+               uint64_t reserved_17_19:3;
+               uint64_t qlm_cfg:1;
+               uint64_t reserved_21_23:3;
+               uint64_t halt:1;
+               uint64_t reserved_25_63:39;
+#endif
        } cn63xx;
        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
        struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
+       struct cvmx_dpi_sli_prtx_cfg_s cnf71xx;
 };
 
 union cvmx_dpi_sli_prtx_err {
        uint64_t u64;
        struct cvmx_dpi_sli_prtx_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t addr:61;
                uint64_t reserved_0_2:3;
+#else
+               uint64_t reserved_0_2:3;
+               uint64_t addr:61;
+#endif
        } s;
        struct cvmx_dpi_sli_prtx_err_s cn61xx;
        struct cvmx_dpi_sli_prtx_err_s cn63xx;
@@ -620,17 +1018,27 @@ union cvmx_dpi_sli_prtx_err {
        struct cvmx_dpi_sli_prtx_err_s cn66xx;
        struct cvmx_dpi_sli_prtx_err_s cn68xx;
        struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
+       struct cvmx_dpi_sli_prtx_err_s cnf71xx;
 };
 
 union cvmx_dpi_sli_prtx_err_info {
        uint64_t u64;
        struct cvmx_dpi_sli_prtx_err_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t lock:1;
                uint64_t reserved_5_7:3;
                uint64_t type:1;
                uint64_t reserved_3_3:1;
                uint64_t reqq:3;
+#else
+               uint64_t reqq:3;
+               uint64_t reserved_3_3:1;
+               uint64_t type:1;
+               uint64_t reserved_5_7:3;
+               uint64_t lock:1;
+               uint64_t reserved_9_63:55;
+#endif
        } s;
        struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
        struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
@@ -638,6 +1046,7 @@ union cvmx_dpi_sli_prtx_err_info {
        struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
        struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
        struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
+       struct cvmx_dpi_sli_prtx_err_info_s cnf71xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h 
b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
index bf5546b..1d79e3c 100644
--- a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,74 +28,83 @@
 #ifndef __CVMX_FPA_DEFS_H__
 #define __CVMX_FPA_DEFS_H__
 
-#define CVMX_FPA_BIST_STATUS \
-        CVMX_ADD_IO_SEG(0x00011800280000E8ull)
-#define CVMX_FPA_CTL_STATUS \
-        CVMX_ADD_IO_SEG(0x0001180028000050ull)
-#define CVMX_FPA_FPF0_MARKS \
-        CVMX_ADD_IO_SEG(0x0001180028000000ull)
-#define CVMX_FPA_FPF0_SIZE \
-        CVMX_ADD_IO_SEG(0x0001180028000058ull)
-#define CVMX_FPA_FPF1_MARKS \
-        CVMX_ADD_IO_SEG(0x0001180028000008ull)
-#define CVMX_FPA_FPF2_MARKS \
-        CVMX_ADD_IO_SEG(0x0001180028000010ull)
-#define CVMX_FPA_FPF3_MARKS \
-        CVMX_ADD_IO_SEG(0x0001180028000018ull)
-#define CVMX_FPA_FPF4_MARKS \
-        CVMX_ADD_IO_SEG(0x0001180028000020ull)
-#define CVMX_FPA_FPF5_MARKS \
-        CVMX_ADD_IO_SEG(0x0001180028000028ull)
-#define CVMX_FPA_FPF6_MARKS \
-        CVMX_ADD_IO_SEG(0x0001180028000030ull)
-#define CVMX_FPA_FPF7_MARKS \
-        CVMX_ADD_IO_SEG(0x0001180028000038ull)
-#define CVMX_FPA_FPFX_MARKS(offset) \
-        CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1)
-#define CVMX_FPA_FPFX_SIZE(offset) \
-        CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1)
-#define CVMX_FPA_INT_ENB \
-        CVMX_ADD_IO_SEG(0x0001180028000048ull)
-#define CVMX_FPA_INT_SUM \
-        CVMX_ADD_IO_SEG(0x0001180028000040ull)
-#define CVMX_FPA_QUE0_PAGE_INDEX \
-        CVMX_ADD_IO_SEG(0x00011800280000F0ull)
-#define CVMX_FPA_QUE1_PAGE_INDEX \
-        CVMX_ADD_IO_SEG(0x00011800280000F8ull)
-#define CVMX_FPA_QUE2_PAGE_INDEX \
-        CVMX_ADD_IO_SEG(0x0001180028000100ull)
-#define CVMX_FPA_QUE3_PAGE_INDEX \
-        CVMX_ADD_IO_SEG(0x0001180028000108ull)
-#define CVMX_FPA_QUE4_PAGE_INDEX \
-        CVMX_ADD_IO_SEG(0x0001180028000110ull)
-#define CVMX_FPA_QUE5_PAGE_INDEX \
-        CVMX_ADD_IO_SEG(0x0001180028000118ull)
-#define CVMX_FPA_QUE6_PAGE_INDEX \
-        CVMX_ADD_IO_SEG(0x0001180028000120ull)
-#define CVMX_FPA_QUE7_PAGE_INDEX \
-        CVMX_ADD_IO_SEG(0x0001180028000128ull)
-#define CVMX_FPA_QUEX_AVAILABLE(offset) \
-        CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8))
-#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \
-        CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8))
-#define CVMX_FPA_QUE_ACT \
-        CVMX_ADD_IO_SEG(0x0001180028000138ull)
-#define CVMX_FPA_QUE_EXP \
-        CVMX_ADD_IO_SEG(0x0001180028000130ull)
-#define CVMX_FPA_WART_CTL \
-        CVMX_ADD_IO_SEG(0x00011800280000D8ull)
-#define CVMX_FPA_WART_STATUS \
-        CVMX_ADD_IO_SEG(0x00011800280000E0ull)
+#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull))
+#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull))
+#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull))
+#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull))
+#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull))
+#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
+#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
+#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
+#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
+#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
+#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
+#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
+#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull))
+#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull))
+#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + 
((offset) & 7) * 8 - 8*1)
+#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + 
((offset) & 7) * 8 - 8*1)
+#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull))
+#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull))
+#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull))
+#define CVMX_FPA_POOLX_END_ADDR(offset) 
(CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8)
+#define CVMX_FPA_POOLX_START_ADDR(offset) 
(CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8)
+#define CVMX_FPA_POOLX_THRESHOLD(offset) 
(CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8)
+#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
+#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
+#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2)
+#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3)
+#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4)
+#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5)
+#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
+#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
+#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull))
+#define CVMX_FPA_QUEX_AVAILABLE(offset) 
(CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8)
+#define CVMX_FPA_QUEX_PAGE_INDEX(offset) 
(CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8)
+#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull))
+#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull))
+#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull))
+#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull))
+#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull))
+
+union cvmx_fpa_addr_range_error {
+       uint64_t u64;
+       struct cvmx_fpa_addr_range_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_38_63:26;
+               uint64_t pool:5;
+               uint64_t addr:33;
+#else
+               uint64_t addr:33;
+               uint64_t pool:5;
+               uint64_t reserved_38_63:26;
+#endif
+       } s;
+       struct cvmx_fpa_addr_range_error_s cn61xx;
+       struct cvmx_fpa_addr_range_error_s cn66xx;
+       struct cvmx_fpa_addr_range_error_s cn68xx;
+       struct cvmx_fpa_addr_range_error_s cn68xxp1;
+       struct cvmx_fpa_addr_range_error_s cnf71xx;
+};
 
 union cvmx_fpa_bist_status {
        uint64_t u64;
        struct cvmx_fpa_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t frd:1;
                uint64_t fpf0:1;
                uint64_t fpf1:1;
                uint64_t ffr:1;
                uint64_t fdr:1;
+#else
+               uint64_t fdr:1;
+               uint64_t ffr:1;
+               uint64_t fpf1:1;
+               uint64_t fpf0:1;
+               uint64_t frd:1;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_fpa_bist_status_s cn30xx;
        struct cvmx_fpa_bist_status_s cn31xx;
@@ -108,38 +117,92 @@ union cvmx_fpa_bist_status {
        struct cvmx_fpa_bist_status_s cn56xxp1;
        struct cvmx_fpa_bist_status_s cn58xx;
        struct cvmx_fpa_bist_status_s cn58xxp1;
+       struct cvmx_fpa_bist_status_s cn61xx;
+       struct cvmx_fpa_bist_status_s cn63xx;
+       struct cvmx_fpa_bist_status_s cn63xxp1;
+       struct cvmx_fpa_bist_status_s cn66xx;
+       struct cvmx_fpa_bist_status_s cn68xx;
+       struct cvmx_fpa_bist_status_s cn68xxp1;
+       struct cvmx_fpa_bist_status_s cnf71xx;
 };
 
 union cvmx_fpa_ctl_status {
        uint64_t u64;
        struct cvmx_fpa_ctl_status_s {
-               uint64_t reserved_18_63:46;
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_21_63:43;
+               uint64_t free_en:1;
+               uint64_t ret_off:1;
+               uint64_t req_off:1;
                uint64_t reset:1;
                uint64_t use_ldt:1;
                uint64_t use_stt:1;
                uint64_t enb:1;
                uint64_t mem1_err:7;
                uint64_t mem0_err:7;
+#else
+               uint64_t mem0_err:7;
+               uint64_t mem1_err:7;
+               uint64_t enb:1;
+               uint64_t use_stt:1;
+               uint64_t use_ldt:1;
+               uint64_t reset:1;
+               uint64_t req_off:1;
+               uint64_t ret_off:1;
+               uint64_t free_en:1;
+               uint64_t reserved_21_63:43;
+#endif
        } s;
-       struct cvmx_fpa_ctl_status_s cn30xx;
-       struct cvmx_fpa_ctl_status_s cn31xx;
-       struct cvmx_fpa_ctl_status_s cn38xx;
-       struct cvmx_fpa_ctl_status_s cn38xxp2;
-       struct cvmx_fpa_ctl_status_s cn50xx;
-       struct cvmx_fpa_ctl_status_s cn52xx;
-       struct cvmx_fpa_ctl_status_s cn52xxp1;
-       struct cvmx_fpa_ctl_status_s cn56xx;
-       struct cvmx_fpa_ctl_status_s cn56xxp1;
-       struct cvmx_fpa_ctl_status_s cn58xx;
-       struct cvmx_fpa_ctl_status_s cn58xxp1;
+       struct cvmx_fpa_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_18_63:46;
+               uint64_t reset:1;
+               uint64_t use_ldt:1;
+               uint64_t use_stt:1;
+               uint64_t enb:1;
+               uint64_t mem1_err:7;
+               uint64_t mem0_err:7;
+#else
+               uint64_t mem0_err:7;
+               uint64_t mem1_err:7;
+               uint64_t enb:1;
+               uint64_t use_stt:1;
+               uint64_t use_ldt:1;
+               uint64_t reset:1;
+               uint64_t reserved_18_63:46;
+#endif
+       } cn30xx;
+       struct cvmx_fpa_ctl_status_cn30xx cn31xx;
+       struct cvmx_fpa_ctl_status_cn30xx cn38xx;
+       struct cvmx_fpa_ctl_status_cn30xx cn38xxp2;
+       struct cvmx_fpa_ctl_status_cn30xx cn50xx;
+       struct cvmx_fpa_ctl_status_cn30xx cn52xx;
+       struct cvmx_fpa_ctl_status_cn30xx cn52xxp1;
+       struct cvmx_fpa_ctl_status_cn30xx cn56xx;
+       struct cvmx_fpa_ctl_status_cn30xx cn56xxp1;
+       struct cvmx_fpa_ctl_status_cn30xx cn58xx;
+       struct cvmx_fpa_ctl_status_cn30xx cn58xxp1;
+       struct cvmx_fpa_ctl_status_s cn61xx;
+       struct cvmx_fpa_ctl_status_s cn63xx;
+       struct cvmx_fpa_ctl_status_cn30xx cn63xxp1;
+       struct cvmx_fpa_ctl_status_s cn66xx;
+       struct cvmx_fpa_ctl_status_s cn68xx;
+       struct cvmx_fpa_ctl_status_s cn68xxp1;
+       struct cvmx_fpa_ctl_status_s cnf71xx;
 };
 
 union cvmx_fpa_fpfx_marks {
        uint64_t u64;
        struct cvmx_fpa_fpfx_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_22_63:42;
                uint64_t fpf_wr:11;
                uint64_t fpf_rd:11;
+#else
+               uint64_t fpf_rd:11;
+               uint64_t fpf_wr:11;
+               uint64_t reserved_22_63:42;
+#endif
        } s;
        struct cvmx_fpa_fpfx_marks_s cn38xx;
        struct cvmx_fpa_fpfx_marks_s cn38xxp2;
@@ -147,13 +210,25 @@ union cvmx_fpa_fpfx_marks {
        struct cvmx_fpa_fpfx_marks_s cn56xxp1;
        struct cvmx_fpa_fpfx_marks_s cn58xx;
        struct cvmx_fpa_fpfx_marks_s cn58xxp1;
+       struct cvmx_fpa_fpfx_marks_s cn61xx;
+       struct cvmx_fpa_fpfx_marks_s cn63xx;
+       struct cvmx_fpa_fpfx_marks_s cn63xxp1;
+       struct cvmx_fpa_fpfx_marks_s cn66xx;
+       struct cvmx_fpa_fpfx_marks_s cn68xx;
+       struct cvmx_fpa_fpfx_marks_s cn68xxp1;
+       struct cvmx_fpa_fpfx_marks_s cnf71xx;
 };
 
 union cvmx_fpa_fpfx_size {
        uint64_t u64;
        struct cvmx_fpa_fpfx_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_11_63:53;
                uint64_t fpf_siz:11;
+#else
+               uint64_t fpf_siz:11;
+               uint64_t reserved_11_63:53;
+#endif
        } s;
        struct cvmx_fpa_fpfx_size_s cn38xx;
        struct cvmx_fpa_fpfx_size_s cn38xxp2;
@@ -161,14 +236,27 @@ union cvmx_fpa_fpfx_size {
        struct cvmx_fpa_fpfx_size_s cn56xxp1;
        struct cvmx_fpa_fpfx_size_s cn58xx;
        struct cvmx_fpa_fpfx_size_s cn58xxp1;
+       struct cvmx_fpa_fpfx_size_s cn61xx;
+       struct cvmx_fpa_fpfx_size_s cn63xx;
+       struct cvmx_fpa_fpfx_size_s cn63xxp1;
+       struct cvmx_fpa_fpfx_size_s cn66xx;
+       struct cvmx_fpa_fpfx_size_s cn68xx;
+       struct cvmx_fpa_fpfx_size_s cn68xxp1;
+       struct cvmx_fpa_fpfx_size_s cnf71xx;
 };
 
 union cvmx_fpa_fpf0_marks {
        uint64_t u64;
        struct cvmx_fpa_fpf0_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_24_63:40;
                uint64_t fpf_wr:12;
                uint64_t fpf_rd:12;
+#else
+               uint64_t fpf_rd:12;
+               uint64_t fpf_wr:12;
+               uint64_t reserved_24_63:40;
+#endif
        } s;
        struct cvmx_fpa_fpf0_marks_s cn38xx;
        struct cvmx_fpa_fpf0_marks_s cn38xxp2;
@@ -176,13 +264,25 @@ union cvmx_fpa_fpf0_marks {
        struct cvmx_fpa_fpf0_marks_s cn56xxp1;
        struct cvmx_fpa_fpf0_marks_s cn58xx;
        struct cvmx_fpa_fpf0_marks_s cn58xxp1;
+       struct cvmx_fpa_fpf0_marks_s cn61xx;
+       struct cvmx_fpa_fpf0_marks_s cn63xx;
+       struct cvmx_fpa_fpf0_marks_s cn63xxp1;
+       struct cvmx_fpa_fpf0_marks_s cn66xx;
+       struct cvmx_fpa_fpf0_marks_s cn68xx;
+       struct cvmx_fpa_fpf0_marks_s cn68xxp1;
+       struct cvmx_fpa_fpf0_marks_s cnf71xx;
 };
 
 union cvmx_fpa_fpf0_size {
        uint64_t u64;
        struct cvmx_fpa_fpf0_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_12_63:52;
                uint64_t fpf_siz:12;
+#else
+               uint64_t fpf_siz:12;
+               uint64_t reserved_12_63:52;
+#endif
        } s;
        struct cvmx_fpa_fpf0_size_s cn38xx;
        struct cvmx_fpa_fpf0_size_s cn38xxp2;
@@ -190,12 +290,555 @@ union cvmx_fpa_fpf0_size {
        struct cvmx_fpa_fpf0_size_s cn56xxp1;
        struct cvmx_fpa_fpf0_size_s cn58xx;
        struct cvmx_fpa_fpf0_size_s cn58xxp1;
+       struct cvmx_fpa_fpf0_size_s cn61xx;
+       struct cvmx_fpa_fpf0_size_s cn63xx;
+       struct cvmx_fpa_fpf0_size_s cn63xxp1;
+       struct cvmx_fpa_fpf0_size_s cn66xx;
+       struct cvmx_fpa_fpf0_size_s cn68xx;
+       struct cvmx_fpa_fpf0_size_s cn68xxp1;
+       struct cvmx_fpa_fpf0_size_s cnf71xx;
+};
+
+union cvmx_fpa_fpf8_marks {
+       uint64_t u64;
+       struct cvmx_fpa_fpf8_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_22_63:42;
+               uint64_t fpf_wr:11;
+               uint64_t fpf_rd:11;
+#else
+               uint64_t fpf_rd:11;
+               uint64_t fpf_wr:11;
+               uint64_t reserved_22_63:42;
+#endif
+       } s;
+       struct cvmx_fpa_fpf8_marks_s cn68xx;
+       struct cvmx_fpa_fpf8_marks_s cn68xxp1;
+};
+
+union cvmx_fpa_fpf8_size {
+       uint64_t u64;
+       struct cvmx_fpa_fpf8_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t fpf_siz:12;
+#else
+               uint64_t fpf_siz:12;
+               uint64_t reserved_12_63:52;
+#endif
+       } s;
+       struct cvmx_fpa_fpf8_size_s cn68xx;
+       struct cvmx_fpa_fpf8_size_s cn68xxp1;
+};
+
+union cvmx_fpa_int_enb {
+       uint64_t u64;
+       struct cvmx_fpa_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_50_63:14;
+               uint64_t paddr_e:1;
+               uint64_t reserved_44_48:5;
+               uint64_t free7:1;
+               uint64_t free6:1;
+               uint64_t free5:1;
+               uint64_t free4:1;
+               uint64_t free3:1;
+               uint64_t free2:1;
+               uint64_t free1:1;
+               uint64_t free0:1;
+               uint64_t pool7th:1;
+               uint64_t pool6th:1;
+               uint64_t pool5th:1;
+               uint64_t pool4th:1;
+               uint64_t pool3th:1;
+               uint64_t pool2th:1;
+               uint64_t pool1th:1;
+               uint64_t pool0th:1;
+               uint64_t q7_perr:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_und:1;
+               uint64_t q6_perr:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_und:1;
+               uint64_t q5_perr:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_und:1;
+               uint64_t q4_perr:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_und:1;
+               uint64_t q3_perr:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_und:1;
+               uint64_t q2_perr:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_und:1;
+               uint64_t q1_perr:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_und:1;
+               uint64_t q0_perr:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_und:1;
+               uint64_t fed1_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed0_sbe:1;
+#else
+               uint64_t fed0_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed1_dbe:1;
+               uint64_t q0_und:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_perr:1;
+               uint64_t q1_und:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_perr:1;
+               uint64_t q2_und:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_perr:1;
+               uint64_t q3_und:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_perr:1;
+               uint64_t q4_und:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_perr:1;
+               uint64_t q5_und:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_perr:1;
+               uint64_t q6_und:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_perr:1;
+               uint64_t q7_und:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_perr:1;
+               uint64_t pool0th:1;
+               uint64_t pool1th:1;
+               uint64_t pool2th:1;
+               uint64_t pool3th:1;
+               uint64_t pool4th:1;
+               uint64_t pool5th:1;
+               uint64_t pool6th:1;
+               uint64_t pool7th:1;
+               uint64_t free0:1;
+               uint64_t free1:1;
+               uint64_t free2:1;
+               uint64_t free3:1;
+               uint64_t free4:1;
+               uint64_t free5:1;
+               uint64_t free6:1;
+               uint64_t free7:1;
+               uint64_t reserved_44_48:5;
+               uint64_t paddr_e:1;
+               uint64_t reserved_50_63:14;
+#endif
+       } s;
+       struct cvmx_fpa_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_28_63:36;
+               uint64_t q7_perr:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_und:1;
+               uint64_t q6_perr:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_und:1;
+               uint64_t q5_perr:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_und:1;
+               uint64_t q4_perr:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_und:1;
+               uint64_t q3_perr:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_und:1;
+               uint64_t q2_perr:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_und:1;
+               uint64_t q1_perr:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_und:1;
+               uint64_t q0_perr:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_und:1;
+               uint64_t fed1_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed0_sbe:1;
+#else
+               uint64_t fed0_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed1_dbe:1;
+               uint64_t q0_und:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_perr:1;
+               uint64_t q1_und:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_perr:1;
+               uint64_t q2_und:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_perr:1;
+               uint64_t q3_und:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_perr:1;
+               uint64_t q4_und:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_perr:1;
+               uint64_t q5_und:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_perr:1;
+               uint64_t q6_und:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_perr:1;
+               uint64_t q7_und:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_perr:1;
+               uint64_t reserved_28_63:36;
+#endif
+       } cn30xx;
+       struct cvmx_fpa_int_enb_cn30xx cn31xx;
+       struct cvmx_fpa_int_enb_cn30xx cn38xx;
+       struct cvmx_fpa_int_enb_cn30xx cn38xxp2;
+       struct cvmx_fpa_int_enb_cn30xx cn50xx;
+       struct cvmx_fpa_int_enb_cn30xx cn52xx;
+       struct cvmx_fpa_int_enb_cn30xx cn52xxp1;
+       struct cvmx_fpa_int_enb_cn30xx cn56xx;
+       struct cvmx_fpa_int_enb_cn30xx cn56xxp1;
+       struct cvmx_fpa_int_enb_cn30xx cn58xx;
+       struct cvmx_fpa_int_enb_cn30xx cn58xxp1;
+       struct cvmx_fpa_int_enb_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_50_63:14;
+               uint64_t paddr_e:1;
+               uint64_t res_44:5;
+               uint64_t free7:1;
+               uint64_t free6:1;
+               uint64_t free5:1;
+               uint64_t free4:1;
+               uint64_t free3:1;
+               uint64_t free2:1;
+               uint64_t free1:1;
+               uint64_t free0:1;
+               uint64_t pool7th:1;
+               uint64_t pool6th:1;
+               uint64_t pool5th:1;
+               uint64_t pool4th:1;
+               uint64_t pool3th:1;
+               uint64_t pool2th:1;
+               uint64_t pool1th:1;
+               uint64_t pool0th:1;
+               uint64_t q7_perr:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_und:1;
+               uint64_t q6_perr:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_und:1;
+               uint64_t q5_perr:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_und:1;
+               uint64_t q4_perr:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_und:1;
+               uint64_t q3_perr:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_und:1;
+               uint64_t q2_perr:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_und:1;
+               uint64_t q1_perr:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_und:1;
+               uint64_t q0_perr:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_und:1;
+               uint64_t fed1_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed0_sbe:1;
+#else
+               uint64_t fed0_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed1_dbe:1;
+               uint64_t q0_und:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_perr:1;
+               uint64_t q1_und:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_perr:1;
+               uint64_t q2_und:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_perr:1;
+               uint64_t q3_und:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_perr:1;
+               uint64_t q4_und:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_perr:1;
+               uint64_t q5_und:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_perr:1;
+               uint64_t q6_und:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_perr:1;
+               uint64_t q7_und:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_perr:1;
+               uint64_t pool0th:1;
+               uint64_t pool1th:1;
+               uint64_t pool2th:1;
+               uint64_t pool3th:1;
+               uint64_t pool4th:1;
+               uint64_t pool5th:1;
+               uint64_t pool6th:1;
+               uint64_t pool7th:1;
+               uint64_t free0:1;
+               uint64_t free1:1;
+               uint64_t free2:1;
+               uint64_t free3:1;
+               uint64_t free4:1;
+               uint64_t free5:1;
+               uint64_t free6:1;
+               uint64_t free7:1;
+               uint64_t res_44:5;
+               uint64_t paddr_e:1;
+               uint64_t reserved_50_63:14;
+#endif
+       } cn61xx;
+       struct cvmx_fpa_int_enb_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_44_63:20;
+               uint64_t free7:1;
+               uint64_t free6:1;
+               uint64_t free5:1;
+               uint64_t free4:1;
+               uint64_t free3:1;
+               uint64_t free2:1;
+               uint64_t free1:1;
+               uint64_t free0:1;
+               uint64_t pool7th:1;
+               uint64_t pool6th:1;
+               uint64_t pool5th:1;
+               uint64_t pool4th:1;
+               uint64_t pool3th:1;
+               uint64_t pool2th:1;
+               uint64_t pool1th:1;
+               uint64_t pool0th:1;
+               uint64_t q7_perr:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_und:1;
+               uint64_t q6_perr:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_und:1;
+               uint64_t q5_perr:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_und:1;
+               uint64_t q4_perr:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_und:1;
+               uint64_t q3_perr:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_und:1;
+               uint64_t q2_perr:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_und:1;
+               uint64_t q1_perr:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_und:1;
+               uint64_t q0_perr:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_und:1;
+               uint64_t fed1_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed0_sbe:1;
+#else
+               uint64_t fed0_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed1_dbe:1;
+               uint64_t q0_und:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_perr:1;
+               uint64_t q1_und:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_perr:1;
+               uint64_t q2_und:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_perr:1;
+               uint64_t q3_und:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_perr:1;
+               uint64_t q4_und:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_perr:1;
+               uint64_t q5_und:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_perr:1;
+               uint64_t q6_und:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_perr:1;
+               uint64_t q7_und:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_perr:1;
+               uint64_t pool0th:1;
+               uint64_t pool1th:1;
+               uint64_t pool2th:1;
+               uint64_t pool3th:1;
+               uint64_t pool4th:1;
+               uint64_t pool5th:1;
+               uint64_t pool6th:1;
+               uint64_t pool7th:1;
+               uint64_t free0:1;
+               uint64_t free1:1;
+               uint64_t free2:1;
+               uint64_t free3:1;
+               uint64_t free4:1;
+               uint64_t free5:1;
+               uint64_t free6:1;
+               uint64_t free7:1;
+               uint64_t reserved_44_63:20;
+#endif
+       } cn63xx;
+       struct cvmx_fpa_int_enb_cn30xx cn63xxp1;
+       struct cvmx_fpa_int_enb_cn61xx cn66xx;
+       struct cvmx_fpa_int_enb_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_50_63:14;
+               uint64_t paddr_e:1;
+               uint64_t pool8th:1;
+               uint64_t q8_perr:1;
+               uint64_t q8_coff:1;
+               uint64_t q8_und:1;
+               uint64_t free8:1;
+               uint64_t free7:1;
+               uint64_t free6:1;
+               uint64_t free5:1;
+               uint64_t free4:1;
+               uint64_t free3:1;
+               uint64_t free2:1;
+               uint64_t free1:1;
+               uint64_t free0:1;
+               uint64_t pool7th:1;
+               uint64_t pool6th:1;
+               uint64_t pool5th:1;
+               uint64_t pool4th:1;
+               uint64_t pool3th:1;
+               uint64_t pool2th:1;
+               uint64_t pool1th:1;
+               uint64_t pool0th:1;
+               uint64_t q7_perr:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_und:1;
+               uint64_t q6_perr:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_und:1;
+               uint64_t q5_perr:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_und:1;
+               uint64_t q4_perr:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_und:1;
+               uint64_t q3_perr:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_und:1;
+               uint64_t q2_perr:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_und:1;
+               uint64_t q1_perr:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_und:1;
+               uint64_t q0_perr:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_und:1;
+               uint64_t fed1_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed0_sbe:1;
+#else
+               uint64_t fed0_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed1_dbe:1;
+               uint64_t q0_und:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_perr:1;
+               uint64_t q1_und:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_perr:1;
+               uint64_t q2_und:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_perr:1;
+               uint64_t q3_und:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_perr:1;
+               uint64_t q4_und:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_perr:1;
+               uint64_t q5_und:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_perr:1;
+               uint64_t q6_und:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_perr:1;
+               uint64_t q7_und:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_perr:1;
+               uint64_t pool0th:1;
+               uint64_t pool1th:1;
+               uint64_t pool2th:1;
+               uint64_t pool3th:1;
+               uint64_t pool4th:1;
+               uint64_t pool5th:1;
+               uint64_t pool6th:1;
+               uint64_t pool7th:1;
+               uint64_t free0:1;
+               uint64_t free1:1;
+               uint64_t free2:1;
+               uint64_t free3:1;
+               uint64_t free4:1;
+               uint64_t free5:1;
+               uint64_t free6:1;
+               uint64_t free7:1;
+               uint64_t free8:1;
+               uint64_t q8_und:1;
+               uint64_t q8_coff:1;
+               uint64_t q8_perr:1;
+               uint64_t pool8th:1;
+               uint64_t paddr_e:1;
+               uint64_t reserved_50_63:14;
+#endif
+       } cn68xx;
+       struct cvmx_fpa_int_enb_cn68xx cn68xxp1;
+       struct cvmx_fpa_int_enb_cn61xx cnf71xx;
 };
 
-union cvmx_fpa_int_enb {
+union cvmx_fpa_int_sum {
        uint64_t u64;
-       struct cvmx_fpa_int_enb_s {
-               uint64_t reserved_28_63:36;
+       struct cvmx_fpa_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_50_63:14;
+               uint64_t paddr_e:1;
+               uint64_t pool8th:1;
+               uint64_t q8_perr:1;
+               uint64_t q8_coff:1;
+               uint64_t q8_und:1;
+               uint64_t free8:1;
+               uint64_t free7:1;
+               uint64_t free6:1;
+               uint64_t free5:1;
+               uint64_t free4:1;
+               uint64_t free3:1;
+               uint64_t free2:1;
+               uint64_t free1:1;
+               uint64_t free0:1;
+               uint64_t pool7th:1;
+               uint64_t pool6th:1;
+               uint64_t pool5th:1;
+               uint64_t pool4th:1;
+               uint64_t pool3th:1;
+               uint64_t pool2th:1;
+               uint64_t pool1th:1;
+               uint64_t pool0th:1;
                uint64_t q7_perr:1;
                uint64_t q7_coff:1;
                uint64_t q7_und:1;
@@ -224,24 +867,251 @@ union cvmx_fpa_int_enb {
                uint64_t fed1_sbe:1;
                uint64_t fed0_dbe:1;
                uint64_t fed0_sbe:1;
+#else
+               uint64_t fed0_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed1_dbe:1;
+               uint64_t q0_und:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_perr:1;
+               uint64_t q1_und:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_perr:1;
+               uint64_t q2_und:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_perr:1;
+               uint64_t q3_und:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_perr:1;
+               uint64_t q4_und:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_perr:1;
+               uint64_t q5_und:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_perr:1;
+               uint64_t q6_und:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_perr:1;
+               uint64_t q7_und:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_perr:1;
+               uint64_t pool0th:1;
+               uint64_t pool1th:1;
+               uint64_t pool2th:1;
+               uint64_t pool3th:1;
+               uint64_t pool4th:1;
+               uint64_t pool5th:1;
+               uint64_t pool6th:1;
+               uint64_t pool7th:1;
+               uint64_t free0:1;
+               uint64_t free1:1;
+               uint64_t free2:1;
+               uint64_t free3:1;
+               uint64_t free4:1;
+               uint64_t free5:1;
+               uint64_t free6:1;
+               uint64_t free7:1;
+               uint64_t free8:1;
+               uint64_t q8_und:1;
+               uint64_t q8_coff:1;
+               uint64_t q8_perr:1;
+               uint64_t pool8th:1;
+               uint64_t paddr_e:1;
+               uint64_t reserved_50_63:14;
+#endif
        } s;
-       struct cvmx_fpa_int_enb_s cn30xx;
-       struct cvmx_fpa_int_enb_s cn31xx;
-       struct cvmx_fpa_int_enb_s cn38xx;
-       struct cvmx_fpa_int_enb_s cn38xxp2;
-       struct cvmx_fpa_int_enb_s cn50xx;
-       struct cvmx_fpa_int_enb_s cn52xx;
-       struct cvmx_fpa_int_enb_s cn52xxp1;
-       struct cvmx_fpa_int_enb_s cn56xx;
-       struct cvmx_fpa_int_enb_s cn56xxp1;
-       struct cvmx_fpa_int_enb_s cn58xx;
-       struct cvmx_fpa_int_enb_s cn58xxp1;
-};
-
-union cvmx_fpa_int_sum {
-       uint64_t u64;
-       struct cvmx_fpa_int_sum_s {
+       struct cvmx_fpa_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_28_63:36;
+               uint64_t q7_perr:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_und:1;
+               uint64_t q6_perr:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_und:1;
+               uint64_t q5_perr:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_und:1;
+               uint64_t q4_perr:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_und:1;
+               uint64_t q3_perr:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_und:1;
+               uint64_t q2_perr:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_und:1;
+               uint64_t q1_perr:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_und:1;
+               uint64_t q0_perr:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_und:1;
+               uint64_t fed1_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed0_sbe:1;
+#else
+               uint64_t fed0_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed1_dbe:1;
+               uint64_t q0_und:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_perr:1;
+               uint64_t q1_und:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_perr:1;
+               uint64_t q2_und:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_perr:1;
+               uint64_t q3_und:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_perr:1;
+               uint64_t q4_und:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_perr:1;
+               uint64_t q5_und:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_perr:1;
+               uint64_t q6_und:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_perr:1;
+               uint64_t q7_und:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_perr:1;
                uint64_t reserved_28_63:36;
+#endif
+       } cn30xx;
+       struct cvmx_fpa_int_sum_cn30xx cn31xx;
+       struct cvmx_fpa_int_sum_cn30xx cn38xx;
+       struct cvmx_fpa_int_sum_cn30xx cn38xxp2;
+       struct cvmx_fpa_int_sum_cn30xx cn50xx;
+       struct cvmx_fpa_int_sum_cn30xx cn52xx;
+       struct cvmx_fpa_int_sum_cn30xx cn52xxp1;
+       struct cvmx_fpa_int_sum_cn30xx cn56xx;
+       struct cvmx_fpa_int_sum_cn30xx cn56xxp1;
+       struct cvmx_fpa_int_sum_cn30xx cn58xx;
+       struct cvmx_fpa_int_sum_cn30xx cn58xxp1;
+       struct cvmx_fpa_int_sum_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_50_63:14;
+               uint64_t paddr_e:1;
+               uint64_t reserved_44_48:5;
+               uint64_t free7:1;
+               uint64_t free6:1;
+               uint64_t free5:1;
+               uint64_t free4:1;
+               uint64_t free3:1;
+               uint64_t free2:1;
+               uint64_t free1:1;
+               uint64_t free0:1;
+               uint64_t pool7th:1;
+               uint64_t pool6th:1;
+               uint64_t pool5th:1;
+               uint64_t pool4th:1;
+               uint64_t pool3th:1;
+               uint64_t pool2th:1;
+               uint64_t pool1th:1;
+               uint64_t pool0th:1;
+               uint64_t q7_perr:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_und:1;
+               uint64_t q6_perr:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_und:1;
+               uint64_t q5_perr:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_und:1;
+               uint64_t q4_perr:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_und:1;
+               uint64_t q3_perr:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_und:1;
+               uint64_t q2_perr:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_und:1;
+               uint64_t q1_perr:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_und:1;
+               uint64_t q0_perr:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_und:1;
+               uint64_t fed1_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed0_sbe:1;
+#else
+               uint64_t fed0_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed1_dbe:1;
+               uint64_t q0_und:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_perr:1;
+               uint64_t q1_und:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_perr:1;
+               uint64_t q2_und:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_perr:1;
+               uint64_t q3_und:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_perr:1;
+               uint64_t q4_und:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_perr:1;
+               uint64_t q5_und:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_perr:1;
+               uint64_t q6_und:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_perr:1;
+               uint64_t q7_und:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_perr:1;
+               uint64_t pool0th:1;
+               uint64_t pool1th:1;
+               uint64_t pool2th:1;
+               uint64_t pool3th:1;
+               uint64_t pool4th:1;
+               uint64_t pool5th:1;
+               uint64_t pool6th:1;
+               uint64_t pool7th:1;
+               uint64_t free0:1;
+               uint64_t free1:1;
+               uint64_t free2:1;
+               uint64_t free3:1;
+               uint64_t free4:1;
+               uint64_t free5:1;
+               uint64_t free6:1;
+               uint64_t free7:1;
+               uint64_t reserved_44_48:5;
+               uint64_t paddr_e:1;
+               uint64_t reserved_50_63:14;
+#endif
+       } cn61xx;
+       struct cvmx_fpa_int_sum_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_44_63:20;
+               uint64_t free7:1;
+               uint64_t free6:1;
+               uint64_t free5:1;
+               uint64_t free4:1;
+               uint64_t free3:1;
+               uint64_t free2:1;
+               uint64_t free1:1;
+               uint64_t free0:1;
+               uint64_t pool7th:1;
+               uint64_t pool6th:1;
+               uint64_t pool5th:1;
+               uint64_t pool4th:1;
+               uint64_t pool3th:1;
+               uint64_t pool2th:1;
+               uint64_t pool1th:1;
+               uint64_t pool0th:1;
                uint64_t q7_perr:1;
                uint64_t q7_coff:1;
                uint64_t q7_und:1;
@@ -270,44 +1140,192 @@ union cvmx_fpa_int_sum {
                uint64_t fed1_sbe:1;
                uint64_t fed0_dbe:1;
                uint64_t fed0_sbe:1;
+#else
+               uint64_t fed0_sbe:1;
+               uint64_t fed0_dbe:1;
+               uint64_t fed1_sbe:1;
+               uint64_t fed1_dbe:1;
+               uint64_t q0_und:1;
+               uint64_t q0_coff:1;
+               uint64_t q0_perr:1;
+               uint64_t q1_und:1;
+               uint64_t q1_coff:1;
+               uint64_t q1_perr:1;
+               uint64_t q2_und:1;
+               uint64_t q2_coff:1;
+               uint64_t q2_perr:1;
+               uint64_t q3_und:1;
+               uint64_t q3_coff:1;
+               uint64_t q3_perr:1;
+               uint64_t q4_und:1;
+               uint64_t q4_coff:1;
+               uint64_t q4_perr:1;
+               uint64_t q5_und:1;
+               uint64_t q5_coff:1;
+               uint64_t q5_perr:1;
+               uint64_t q6_und:1;
+               uint64_t q6_coff:1;
+               uint64_t q6_perr:1;
+               uint64_t q7_und:1;
+               uint64_t q7_coff:1;
+               uint64_t q7_perr:1;
+               uint64_t pool0th:1;
+               uint64_t pool1th:1;
+               uint64_t pool2th:1;
+               uint64_t pool3th:1;
+               uint64_t pool4th:1;
+               uint64_t pool5th:1;
+               uint64_t pool6th:1;
+               uint64_t pool7th:1;
+               uint64_t free0:1;
+               uint64_t free1:1;
+               uint64_t free2:1;
+               uint64_t free3:1;
+               uint64_t free4:1;
+               uint64_t free5:1;
+               uint64_t free6:1;
+               uint64_t free7:1;
+               uint64_t reserved_44_63:20;
+#endif
+       } cn63xx;
+       struct cvmx_fpa_int_sum_cn30xx cn63xxp1;
+       struct cvmx_fpa_int_sum_cn61xx cn66xx;
+       struct cvmx_fpa_int_sum_s cn68xx;
+       struct cvmx_fpa_int_sum_s cn68xxp1;
+       struct cvmx_fpa_int_sum_cn61xx cnf71xx;
+};
+
+union cvmx_fpa_packet_threshold {
+       uint64_t u64;
+       struct cvmx_fpa_packet_threshold_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t thresh:32;
+#else
+               uint64_t thresh:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_fpa_packet_threshold_s cn61xx;
+       struct cvmx_fpa_packet_threshold_s cn63xx;
+       struct cvmx_fpa_packet_threshold_s cn66xx;
+       struct cvmx_fpa_packet_threshold_s cn68xx;
+       struct cvmx_fpa_packet_threshold_s cn68xxp1;
+       struct cvmx_fpa_packet_threshold_s cnf71xx;
+};
+
+union cvmx_fpa_poolx_end_addr {
+       uint64_t u64;
+       struct cvmx_fpa_poolx_end_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_33_63:31;
+               uint64_t addr:33;
+#else
+               uint64_t addr:33;
+               uint64_t reserved_33_63:31;
+#endif
+       } s;
+       struct cvmx_fpa_poolx_end_addr_s cn61xx;
+       struct cvmx_fpa_poolx_end_addr_s cn66xx;
+       struct cvmx_fpa_poolx_end_addr_s cn68xx;
+       struct cvmx_fpa_poolx_end_addr_s cn68xxp1;
+       struct cvmx_fpa_poolx_end_addr_s cnf71xx;
+};
+
+union cvmx_fpa_poolx_start_addr {
+       uint64_t u64;
+       struct cvmx_fpa_poolx_start_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_33_63:31;
+               uint64_t addr:33;
+#else
+               uint64_t addr:33;
+               uint64_t reserved_33_63:31;
+#endif
+       } s;
+       struct cvmx_fpa_poolx_start_addr_s cn61xx;
+       struct cvmx_fpa_poolx_start_addr_s cn66xx;
+       struct cvmx_fpa_poolx_start_addr_s cn68xx;
+       struct cvmx_fpa_poolx_start_addr_s cn68xxp1;
+       struct cvmx_fpa_poolx_start_addr_s cnf71xx;
+};
+
+union cvmx_fpa_poolx_threshold {
+       uint64_t u64;
+       struct cvmx_fpa_poolx_threshold_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t thresh:32;
+#else
+               uint64_t thresh:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
-       struct cvmx_fpa_int_sum_s cn30xx;
-       struct cvmx_fpa_int_sum_s cn31xx;
-       struct cvmx_fpa_int_sum_s cn38xx;
-       struct cvmx_fpa_int_sum_s cn38xxp2;
-       struct cvmx_fpa_int_sum_s cn50xx;
-       struct cvmx_fpa_int_sum_s cn52xx;
-       struct cvmx_fpa_int_sum_s cn52xxp1;
-       struct cvmx_fpa_int_sum_s cn56xx;
-       struct cvmx_fpa_int_sum_s cn56xxp1;
-       struct cvmx_fpa_int_sum_s cn58xx;
-       struct cvmx_fpa_int_sum_s cn58xxp1;
+       struct cvmx_fpa_poolx_threshold_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_29_63:35;
+               uint64_t thresh:29;
+#else
+               uint64_t thresh:29;
+               uint64_t reserved_29_63:35;
+#endif
+       } cn61xx;
+       struct cvmx_fpa_poolx_threshold_cn61xx cn63xx;
+       struct cvmx_fpa_poolx_threshold_cn61xx cn66xx;
+       struct cvmx_fpa_poolx_threshold_s cn68xx;
+       struct cvmx_fpa_poolx_threshold_s cn68xxp1;
+       struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx;
 };
 
 union cvmx_fpa_quex_available {
        uint64_t u64;
        struct cvmx_fpa_quex_available_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t que_siz:32;
+#else
+               uint64_t que_siz:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_fpa_quex_available_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_29_63:35;
                uint64_t que_siz:29;
-       } s;
-       struct cvmx_fpa_quex_available_s cn30xx;
-       struct cvmx_fpa_quex_available_s cn31xx;
-       struct cvmx_fpa_quex_available_s cn38xx;
-       struct cvmx_fpa_quex_available_s cn38xxp2;
-       struct cvmx_fpa_quex_available_s cn50xx;
-       struct cvmx_fpa_quex_available_s cn52xx;
-       struct cvmx_fpa_quex_available_s cn52xxp1;
-       struct cvmx_fpa_quex_available_s cn56xx;
-       struct cvmx_fpa_quex_available_s cn56xxp1;
-       struct cvmx_fpa_quex_available_s cn58xx;
-       struct cvmx_fpa_quex_available_s cn58xxp1;
+#else
+               uint64_t que_siz:29;
+               uint64_t reserved_29_63:35;
+#endif
+       } cn30xx;
+       struct cvmx_fpa_quex_available_cn30xx cn31xx;
+       struct cvmx_fpa_quex_available_cn30xx cn38xx;
+       struct cvmx_fpa_quex_available_cn30xx cn38xxp2;
+       struct cvmx_fpa_quex_available_cn30xx cn50xx;
+       struct cvmx_fpa_quex_available_cn30xx cn52xx;
+       struct cvmx_fpa_quex_available_cn30xx cn52xxp1;
+       struct cvmx_fpa_quex_available_cn30xx cn56xx;
+       struct cvmx_fpa_quex_available_cn30xx cn56xxp1;
+       struct cvmx_fpa_quex_available_cn30xx cn58xx;
+       struct cvmx_fpa_quex_available_cn30xx cn58xxp1;
+       struct cvmx_fpa_quex_available_cn30xx cn61xx;
+       struct cvmx_fpa_quex_available_cn30xx cn63xx;
+       struct cvmx_fpa_quex_available_cn30xx cn63xxp1;
+       struct cvmx_fpa_quex_available_cn30xx cn66xx;
+       struct cvmx_fpa_quex_available_s cn68xx;
+       struct cvmx_fpa_quex_available_s cn68xxp1;
+       struct cvmx_fpa_quex_available_cn30xx cnf71xx;
 };
 
 union cvmx_fpa_quex_page_index {
        uint64_t u64;
        struct cvmx_fpa_quex_page_index_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_25_63:39;
                uint64_t pg_num:25;
+#else
+               uint64_t pg_num:25;
+               uint64_t reserved_25_63:39;
+#endif
        } s;
        struct cvmx_fpa_quex_page_index_s cn30xx;
        struct cvmx_fpa_quex_page_index_s cn31xx;
@@ -320,14 +1338,42 @@ union cvmx_fpa_quex_page_index {
        struct cvmx_fpa_quex_page_index_s cn56xxp1;
        struct cvmx_fpa_quex_page_index_s cn58xx;
        struct cvmx_fpa_quex_page_index_s cn58xxp1;
+       struct cvmx_fpa_quex_page_index_s cn61xx;
+       struct cvmx_fpa_quex_page_index_s cn63xx;
+       struct cvmx_fpa_quex_page_index_s cn63xxp1;
+       struct cvmx_fpa_quex_page_index_s cn66xx;
+       struct cvmx_fpa_quex_page_index_s cn68xx;
+       struct cvmx_fpa_quex_page_index_s cn68xxp1;
+       struct cvmx_fpa_quex_page_index_s cnf71xx;
+};
+
+union cvmx_fpa_que8_page_index {
+       uint64_t u64;
+       struct cvmx_fpa_que8_page_index_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_25_63:39;
+               uint64_t pg_num:25;
+#else
+               uint64_t pg_num:25;
+               uint64_t reserved_25_63:39;
+#endif
+       } s;
+       struct cvmx_fpa_que8_page_index_s cn68xx;
+       struct cvmx_fpa_que8_page_index_s cn68xxp1;
 };
 
 union cvmx_fpa_que_act {
        uint64_t u64;
        struct cvmx_fpa_que_act_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_29_63:35;
                uint64_t act_que:3;
                uint64_t act_indx:26;
+#else
+               uint64_t act_indx:26;
+               uint64_t act_que:3;
+               uint64_t reserved_29_63:35;
+#endif
        } s;
        struct cvmx_fpa_que_act_s cn30xx;
        struct cvmx_fpa_que_act_s cn31xx;
@@ -340,14 +1386,27 @@ union cvmx_fpa_que_act {
        struct cvmx_fpa_que_act_s cn56xxp1;
        struct cvmx_fpa_que_act_s cn58xx;
        struct cvmx_fpa_que_act_s cn58xxp1;
+       struct cvmx_fpa_que_act_s cn61xx;
+       struct cvmx_fpa_que_act_s cn63xx;
+       struct cvmx_fpa_que_act_s cn63xxp1;
+       struct cvmx_fpa_que_act_s cn66xx;
+       struct cvmx_fpa_que_act_s cn68xx;
+       struct cvmx_fpa_que_act_s cn68xxp1;
+       struct cvmx_fpa_que_act_s cnf71xx;
 };
 
 union cvmx_fpa_que_exp {
        uint64_t u64;
        struct cvmx_fpa_que_exp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_29_63:35;
                uint64_t exp_que:3;
                uint64_t exp_indx:26;
+#else
+               uint64_t exp_indx:26;
+               uint64_t exp_que:3;
+               uint64_t reserved_29_63:35;
+#endif
        } s;
        struct cvmx_fpa_que_exp_s cn30xx;
        struct cvmx_fpa_que_exp_s cn31xx;
@@ -360,13 +1419,25 @@ union cvmx_fpa_que_exp {
        struct cvmx_fpa_que_exp_s cn56xxp1;
        struct cvmx_fpa_que_exp_s cn58xx;
        struct cvmx_fpa_que_exp_s cn58xxp1;
+       struct cvmx_fpa_que_exp_s cn61xx;
+       struct cvmx_fpa_que_exp_s cn63xx;
+       struct cvmx_fpa_que_exp_s cn63xxp1;
+       struct cvmx_fpa_que_exp_s cn66xx;
+       struct cvmx_fpa_que_exp_s cn68xx;
+       struct cvmx_fpa_que_exp_s cn68xxp1;
+       struct cvmx_fpa_que_exp_s cnf71xx;
 };
 
 union cvmx_fpa_wart_ctl {
        uint64_t u64;
        struct cvmx_fpa_wart_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t ctl:16;
+#else
+               uint64_t ctl:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_fpa_wart_ctl_s cn30xx;
        struct cvmx_fpa_wart_ctl_s cn31xx;
@@ -384,8 +1455,13 @@ union cvmx_fpa_wart_ctl {
 union cvmx_fpa_wart_status {
        uint64_t u64;
        struct cvmx_fpa_wart_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t status:32;
+#else
+               uint64_t status:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_fpa_wart_status_s cn30xx;
        struct cvmx_fpa_wart_status_s cn31xx;
@@ -400,4 +1476,23 @@ union cvmx_fpa_wart_status {
        struct cvmx_fpa_wart_status_s cn58xxp1;
 };
 
+union cvmx_fpa_wqe_threshold {
+       uint64_t u64;
+       struct cvmx_fpa_wqe_threshold_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t thresh:32;
+#else
+               uint64_t thresh:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_fpa_wqe_threshold_s cn61xx;
+       struct cvmx_fpa_wqe_threshold_s cn63xx;
+       struct cvmx_fpa_wqe_threshold_s cn66xx;
+       struct cvmx_fpa_wqe_threshold_s cn68xx;
+       struct cvmx_fpa_wqe_threshold_s cn68xxp1;
+       struct cvmx_fpa_wqe_threshold_s cnf71xx;
+};
+
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h 
b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
index 946a43a..e347496 100644
--- a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,208 +28,2052 @@
 #ifndef __CVMX_GMXX_DEFS_H__
 #define __CVMX_GMXX_DEFS_H__
 
-#define CVMX_GMXX_BAD_REG(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_BIST(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_CLK_EN(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_HG2_CONTROL(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_INF_MODE(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_NXA_ADR(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_PRTX_CFG(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_DECISION(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_IFG(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_JABBER(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RX_HG2_STATUS(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_RX_PASS_EN(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_RX_PRTS(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_RX_PRT_INFO(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_RX_TX_STATUS(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 
0x8000000ull))
-#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_RX_XAUI_CTL(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_SMACX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_STAT_BP(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TXX_APPEND(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_BURST(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_CLK(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_CTL(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_SLOT(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STAT0(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STAT1(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STAT2(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STAT3(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STAT4(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STAT5(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STAT6(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STAT7(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STAT8(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STAT9(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TXX_THRESH(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TX_BP(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + 
(((block_id) & 0) * 0x0ull))
-#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_CORRUPT(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_HG2_REG1(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_HG2_REG2(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_IFG(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_INT_EN(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_INT_REG(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_JAM(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_LFSR(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_OVR_BP(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_PRTS(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_SPI_CTL(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_SPI_MAX(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + 
(((block_id) & 1) * 0x8000000ull))
-#define CVMX_GMXX_TX_SPI_THRESH(block_id) \
-        CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_TX_XAUI_CTL(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 
0x8000000ull))
-#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \
-        CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 
0x8000000ull))
+static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 
0x8000000ull;
+}
+
+#define CVMX_GMXX_BPID_MAPX(offset, block_id) 
(CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 
0x200000ull) * 8)
+#define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + 
((block_id) & 7) * 0x1000000ull)
+static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 
0x8000000ull;
+}
+
+#define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + 
((block_id) & 7) * 0x1000000ull)
+#define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + 
((block_id) & 7) * 0x1000000ull)
+static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 
0x8000000ull;
+}
+
+#define CVMX_GMXX_PIPE_STATUS(block_id) 
(CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull)
+static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+#define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) 
+ ((block_id) & 7) * 0x1000000ull)
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) 
(CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 
0x10000ull) * 2048)
+#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) 
(CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 
0x10000ull) * 2048)
+static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) 
(CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 
0x10000ull) * 2048)
+static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + 
(block_id) * 0x0ull) * 8;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + 
(block_id) * 0x200000ull) * 8;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) 
* 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + 
(block_id) * 0x0ull) * 8;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + 
(block_id) * 0x200000ull) * 8;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) 
* 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + 
(block_id) * 0x1000000ull) * 8;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + 
(block_id) * 0x0ull) * 8;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + 
(block_id) * 0x200000ull) * 8;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) 
* 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 
0x8000000ull;
+}
+
+#define CVMX_GMXX_RX_PASS_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080005F8ull) 
+ ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) 
(CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 
0x1000000ull) * 8)
+static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 
0x8000000ull;
+}
+
+#define CVMX_GMXX_RX_TX_STATUS(block_id) 
(CVMX_ADD_IO_SEG(0x00011800080007E8ull))
+static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 
0x1000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 
0x8000000ull;
+}
+
+#define CVMX_GMXX_TXX_CLK(offset, block_id) 
(CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 
0x10000ull) * 2048)
+static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, 
unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+#define CVMX_GMXX_TXX_PIPE(offset, block_id) 
(CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 
0x2000ull) * 2048)
+static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long 
block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned 
long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + 
(block_id) * 0x10000ull) * 2048;
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + 
(block_id) * 0x0ull) * 2048;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + 
(block_id) * 0x2000ull) * 2048;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) 
* 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 
0x8000000ull;
+}
+
+#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) 
(CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 
0x0ull) * 8)
+static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 
0x8000000ull;
+}
+
+#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) 
+ ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_TX_SPI_DRAIN(block_id) 
(CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) 
+ ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) 
(CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 
0x1000000ull) * 8)
+#define CVMX_GMXX_TX_SPI_THRESH(block_id) 
(CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
+static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 
0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
+{
+       switch (cvmx_get_octeon_family()) {
+       case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+       case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 
0x8000000ull;
+       case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+               return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 
0x1000000ull;
+       }
+       return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 
0x8000000ull;
+}
 
 union cvmx_gmxx_bad_reg {
        uint64_t u64;
        struct cvmx_gmxx_bad_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_31_63:33;
                uint64_t inb_nxa:4;
                uint64_t statovr:1;
@@ -238,8 +2082,19 @@ union cvmx_gmxx_bad_reg {
                uint64_t out_ovr:16;
                uint64_t ncb_ovr:1;
                uint64_t out_col:1;
+#else
+               uint64_t out_col:1;
+               uint64_t ncb_ovr:1;
+               uint64_t out_ovr:16;
+               uint64_t reserved_18_21:4;
+               uint64_t loststat:4;
+               uint64_t statovr:1;
+               uint64_t inb_nxa:4;
+               uint64_t reserved_31_63:33;
+#endif
        } s;
        struct cvmx_gmxx_bad_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_31_63:33;
                uint64_t inb_nxa:4;
                uint64_t statovr:1;
@@ -248,12 +2103,23 @@ union cvmx_gmxx_bad_reg {
                uint64_t reserved_5_21:17;
                uint64_t out_ovr:3;
                uint64_t reserved_0_1:2;
+#else
+               uint64_t reserved_0_1:2;
+               uint64_t out_ovr:3;
+               uint64_t reserved_5_21:17;
+               uint64_t loststat:3;
+               uint64_t reserved_25_25:1;
+               uint64_t statovr:1;
+               uint64_t inb_nxa:4;
+               uint64_t reserved_31_63:33;
+#endif
        } cn30xx;
        struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
        struct cvmx_gmxx_bad_reg_s cn38xx;
        struct cvmx_gmxx_bad_reg_s cn38xxp2;
        struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
        struct cvmx_gmxx_bad_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_31_63:33;
                uint64_t inb_nxa:4;
                uint64_t statovr:1;
@@ -261,95 +2127,274 @@ union cvmx_gmxx_bad_reg {
                uint64_t reserved_6_21:16;
                uint64_t out_ovr:4;
                uint64_t reserved_0_1:2;
+#else
+               uint64_t reserved_0_1:2;
+               uint64_t out_ovr:4;
+               uint64_t reserved_6_21:16;
+               uint64_t loststat:4;
+               uint64_t statovr:1;
+               uint64_t inb_nxa:4;
+               uint64_t reserved_31_63:33;
+#endif
        } cn52xx;
        struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
        struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
        struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
        struct cvmx_gmxx_bad_reg_s cn58xx;
        struct cvmx_gmxx_bad_reg_s cn58xxp1;
+       struct cvmx_gmxx_bad_reg_cn52xx cn61xx;
+       struct cvmx_gmxx_bad_reg_cn52xx cn63xx;
+       struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1;
+       struct cvmx_gmxx_bad_reg_cn52xx cn66xx;
+       struct cvmx_gmxx_bad_reg_cn52xx cn68xx;
+       struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1;
+       struct cvmx_gmxx_bad_reg_cn52xx cnf71xx;
 };
 
 union cvmx_gmxx_bist {
        uint64_t u64;
        struct cvmx_gmxx_bist_s {
-               uint64_t reserved_17_63:47;
-               uint64_t status:17;
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_25_63:39;
+               uint64_t status:25;
+#else
+               uint64_t status:25;
+               uint64_t reserved_25_63:39;
+#endif
        } s;
        struct cvmx_gmxx_bist_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t status:10;
+#else
+               uint64_t status:10;
+               uint64_t reserved_10_63:54;
+#endif
        } cn30xx;
        struct cvmx_gmxx_bist_cn30xx cn31xx;
        struct cvmx_gmxx_bist_cn30xx cn38xx;
        struct cvmx_gmxx_bist_cn30xx cn38xxp2;
        struct cvmx_gmxx_bist_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_12_63:52;
                uint64_t status:12;
+#else
+               uint64_t status:12;
+               uint64_t reserved_12_63:52;
+#endif
        } cn50xx;
        struct cvmx_gmxx_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t status:16;
+#else
+               uint64_t status:16;
+               uint64_t reserved_16_63:48;
+#endif
        } cn52xx;
        struct cvmx_gmxx_bist_cn52xx cn52xxp1;
        struct cvmx_gmxx_bist_cn52xx cn56xx;
        struct cvmx_gmxx_bist_cn52xx cn56xxp1;
-       struct cvmx_gmxx_bist_s cn58xx;
-       struct cvmx_gmxx_bist_s cn58xxp1;
+       struct cvmx_gmxx_bist_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_17_63:47;
+               uint64_t status:17;
+#else
+               uint64_t status:17;
+               uint64_t reserved_17_63:47;
+#endif
+       } cn58xx;
+       struct cvmx_gmxx_bist_cn58xx cn58xxp1;
+       struct cvmx_gmxx_bist_s cn61xx;
+       struct cvmx_gmxx_bist_s cn63xx;
+       struct cvmx_gmxx_bist_s cn63xxp1;
+       struct cvmx_gmxx_bist_s cn66xx;
+       struct cvmx_gmxx_bist_s cn68xx;
+       struct cvmx_gmxx_bist_s cn68xxp1;
+       struct cvmx_gmxx_bist_s cnf71xx;
+};
+
+union cvmx_gmxx_bpid_mapx {
+       uint64_t u64;
+       struct cvmx_gmxx_bpid_mapx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_17_63:47;
+               uint64_t status:1;
+               uint64_t reserved_9_15:7;
+               uint64_t val:1;
+               uint64_t reserved_6_7:2;
+               uint64_t bpid:6;
+#else
+               uint64_t bpid:6;
+               uint64_t reserved_6_7:2;
+               uint64_t val:1;
+               uint64_t reserved_9_15:7;
+               uint64_t status:1;
+               uint64_t reserved_17_63:47;
+#endif
+       } s;
+       struct cvmx_gmxx_bpid_mapx_s cn68xx;
+       struct cvmx_gmxx_bpid_mapx_s cn68xxp1;
+};
+
+union cvmx_gmxx_bpid_msk {
+       uint64_t u64;
+       struct cvmx_gmxx_bpid_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_48_63:16;
+               uint64_t msk_or:16;
+               uint64_t reserved_16_31:16;
+               uint64_t msk_and:16;
+#else
+               uint64_t msk_and:16;
+               uint64_t reserved_16_31:16;
+               uint64_t msk_or:16;
+               uint64_t reserved_48_63:16;
+#endif
+       } s;
+       struct cvmx_gmxx_bpid_msk_s cn68xx;
+       struct cvmx_gmxx_bpid_msk_s cn68xxp1;
 };
 
 union cvmx_gmxx_clk_en {
        uint64_t u64;
        struct cvmx_gmxx_clk_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t clk_en:1;
+#else
+               uint64_t clk_en:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
        struct cvmx_gmxx_clk_en_s cn52xx;
        struct cvmx_gmxx_clk_en_s cn52xxp1;
        struct cvmx_gmxx_clk_en_s cn56xx;
        struct cvmx_gmxx_clk_en_s cn56xxp1;
+       struct cvmx_gmxx_clk_en_s cn61xx;
+       struct cvmx_gmxx_clk_en_s cn63xx;
+       struct cvmx_gmxx_clk_en_s cn63xxp1;
+       struct cvmx_gmxx_clk_en_s cn66xx;
+       struct cvmx_gmxx_clk_en_s cn68xx;
+       struct cvmx_gmxx_clk_en_s cn68xxp1;
+       struct cvmx_gmxx_clk_en_s cnf71xx;
+};
+
+union cvmx_gmxx_ebp_dis {
+       uint64_t u64;
+       struct cvmx_gmxx_ebp_dis_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t dis:16;
+#else
+               uint64_t dis:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_gmxx_ebp_dis_s cn68xx;
+       struct cvmx_gmxx_ebp_dis_s cn68xxp1;
+};
+
+union cvmx_gmxx_ebp_msk {
+       uint64_t u64;
+       struct cvmx_gmxx_ebp_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_16_63:48;
+               uint64_t msk:16;
+#else
+               uint64_t msk:16;
+               uint64_t reserved_16_63:48;
+#endif
+       } s;
+       struct cvmx_gmxx_ebp_msk_s cn68xx;
+       struct cvmx_gmxx_ebp_msk_s cn68xxp1;
 };
 
 union cvmx_gmxx_hg2_control {
        uint64_t u64;
        struct cvmx_gmxx_hg2_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_19_63:45;
                uint64_t hg2tx_en:1;
                uint64_t hg2rx_en:1;
                uint64_t phys_en:1;
                uint64_t logl_en:16;
+#else
+               uint64_t logl_en:16;
+               uint64_t phys_en:1;
+               uint64_t hg2rx_en:1;
+               uint64_t hg2tx_en:1;
+               uint64_t reserved_19_63:45;
+#endif
        } s;
        struct cvmx_gmxx_hg2_control_s cn52xx;
        struct cvmx_gmxx_hg2_control_s cn52xxp1;
        struct cvmx_gmxx_hg2_control_s cn56xx;
+       struct cvmx_gmxx_hg2_control_s cn61xx;
+       struct cvmx_gmxx_hg2_control_s cn63xx;
+       struct cvmx_gmxx_hg2_control_s cn63xxp1;
+       struct cvmx_gmxx_hg2_control_s cn66xx;
+       struct cvmx_gmxx_hg2_control_s cn68xx;
+       struct cvmx_gmxx_hg2_control_s cn68xxp1;
+       struct cvmx_gmxx_hg2_control_s cnf71xx;
 };
 
 union cvmx_gmxx_inf_mode {
        uint64_t u64;
        struct cvmx_gmxx_inf_mode_s {
-               uint64_t reserved_10_63:54;
-               uint64_t speed:2;
-               uint64_t reserved_6_7:2;
-               uint64_t mode:2;
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_20_63:44;
+               uint64_t rate:4;
+               uint64_t reserved_12_15:4;
+               uint64_t speed:4;
+               uint64_t reserved_7_7:1;
+               uint64_t mode:3;
                uint64_t reserved_3_3:1;
                uint64_t p0mii:1;
                uint64_t en:1;
                uint64_t type:1;
+#else
+               uint64_t type:1;
+               uint64_t en:1;
+               uint64_t p0mii:1;
+               uint64_t reserved_3_3:1;
+               uint64_t mode:3;
+               uint64_t reserved_7_7:1;
+               uint64_t speed:4;
+               uint64_t reserved_12_15:4;
+               uint64_t rate:4;
+               uint64_t reserved_20_63:44;
+#endif
        } s;
        struct cvmx_gmxx_inf_mode_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_3_63:61;
                uint64_t p0mii:1;
                uint64_t en:1;
                uint64_t type:1;
+#else
+               uint64_t type:1;
+               uint64_t en:1;
+               uint64_t p0mii:1;
+               uint64_t reserved_3_63:61;
+#endif
        } cn30xx;
        struct cvmx_gmxx_inf_mode_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_2_63:62;
                uint64_t en:1;
                uint64_t type:1;
+#else
+               uint64_t type:1;
+               uint64_t en:1;
+               uint64_t reserved_2_63:62;
+#endif
        } cn31xx;
        struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
        struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
        struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
        struct cvmx_gmxx_inf_mode_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t speed:2;
                uint64_t reserved_6_7:2;
@@ -357,36 +2402,158 @@ union cvmx_gmxx_inf_mode {
                uint64_t reserved_2_3:2;
                uint64_t en:1;
                uint64_t type:1;
+#else
+               uint64_t type:1;
+               uint64_t en:1;
+               uint64_t reserved_2_3:2;
+               uint64_t mode:2;
+               uint64_t reserved_6_7:2;
+               uint64_t speed:2;
+               uint64_t reserved_10_63:54;
+#endif
        } cn52xx;
        struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
        struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
        struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
        struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
        struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
+       struct cvmx_gmxx_inf_mode_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t speed:4;
+               uint64_t reserved_5_7:3;
+               uint64_t mode:1;
+               uint64_t reserved_2_3:2;
+               uint64_t en:1;
+               uint64_t type:1;
+#else
+               uint64_t type:1;
+               uint64_t en:1;
+               uint64_t reserved_2_3:2;
+               uint64_t mode:1;
+               uint64_t reserved_5_7:3;
+               uint64_t speed:4;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn61xx;
+       struct cvmx_gmxx_inf_mode_cn61xx cn63xx;
+       struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1;
+       struct cvmx_gmxx_inf_mode_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_20_63:44;
+               uint64_t rate:4;
+               uint64_t reserved_12_15:4;
+               uint64_t speed:4;
+               uint64_t reserved_5_7:3;
+               uint64_t mode:1;
+               uint64_t reserved_2_3:2;
+               uint64_t en:1;
+               uint64_t type:1;
+#else
+               uint64_t type:1;
+               uint64_t en:1;
+               uint64_t reserved_2_3:2;
+               uint64_t mode:1;
+               uint64_t reserved_5_7:3;
+               uint64_t speed:4;
+               uint64_t reserved_12_15:4;
+               uint64_t rate:4;
+               uint64_t reserved_20_63:44;
+#endif
+       } cn66xx;
+       struct cvmx_gmxx_inf_mode_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_12_63:52;
+               uint64_t speed:4;
+               uint64_t reserved_7_7:1;
+               uint64_t mode:3;
+               uint64_t reserved_2_3:2;
+               uint64_t en:1;
+               uint64_t type:1;
+#else
+               uint64_t type:1;
+               uint64_t en:1;
+               uint64_t reserved_2_3:2;
+               uint64_t mode:3;
+               uint64_t reserved_7_7:1;
+               uint64_t speed:4;
+               uint64_t reserved_12_63:52;
+#endif
+       } cn68xx;
+       struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1;
+       struct cvmx_gmxx_inf_mode_cn61xx cnf71xx;
 };
 
 union cvmx_gmxx_nxa_adr {
        uint64_t u64;
        struct cvmx_gmxx_nxa_adr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_23_63:41;
+               uint64_t pipe:7;
+               uint64_t reserved_6_15:10;
+               uint64_t prt:6;
+#else
+               uint64_t prt:6;
+               uint64_t reserved_6_15:10;
+               uint64_t pipe:7;
+               uint64_t reserved_23_63:41;
+#endif
+       } s;
+       struct cvmx_gmxx_nxa_adr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t prt:6;
+#else
+               uint64_t prt:6;
+               uint64_t reserved_6_63:58;
+#endif
+       } cn30xx;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn31xx;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn38xx;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn50xx;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn52xx;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn56xx;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn58xx;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn61xx;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn63xx;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1;
+       struct cvmx_gmxx_nxa_adr_cn30xx cn66xx;
+       struct cvmx_gmxx_nxa_adr_s cn68xx;
+       struct cvmx_gmxx_nxa_adr_s cn68xxp1;
+       struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx;
+};
+
+union cvmx_gmxx_pipe_status {
+       uint64_t u64;
+       struct cvmx_gmxx_pipe_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_20_63:44;
+               uint64_t ovr:4;
+               uint64_t reserved_12_15:4;
+               uint64_t bp:4;
+               uint64_t reserved_4_7:4;
+               uint64_t stop:4;
+#else
+               uint64_t stop:4;
+               uint64_t reserved_4_7:4;
+               uint64_t bp:4;
+               uint64_t reserved_12_15:4;
+               uint64_t ovr:4;
+               uint64_t reserved_20_63:44;
+#endif
        } s;
-       struct cvmx_gmxx_nxa_adr_s cn30xx;
-       struct cvmx_gmxx_nxa_adr_s cn31xx;
-       struct cvmx_gmxx_nxa_adr_s cn38xx;
-       struct cvmx_gmxx_nxa_adr_s cn38xxp2;
-       struct cvmx_gmxx_nxa_adr_s cn50xx;
-       struct cvmx_gmxx_nxa_adr_s cn52xx;
-       struct cvmx_gmxx_nxa_adr_s cn52xxp1;
-       struct cvmx_gmxx_nxa_adr_s cn56xx;
-       struct cvmx_gmxx_nxa_adr_s cn56xxp1;
-       struct cvmx_gmxx_nxa_adr_s cn58xx;
-       struct cvmx_gmxx_nxa_adr_s cn58xxp1;
+       struct cvmx_gmxx_pipe_status_s cn68xx;
+       struct cvmx_gmxx_pipe_status_s cn68xxp1;
 };
 
 union cvmx_gmxx_prtx_cbfc_ctl {
        uint64_t u64;
        struct cvmx_gmxx_prtx_cbfc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t phys_en:16;
                uint64_t logl_en:16;
                uint64_t phys_bp:16;
@@ -395,15 +2562,35 @@ union cvmx_gmxx_prtx_cbfc_ctl {
                uint64_t drp_en:1;
                uint64_t tx_en:1;
                uint64_t rx_en:1;
+#else
+               uint64_t rx_en:1;
+               uint64_t tx_en:1;
+               uint64_t drp_en:1;
+               uint64_t bck_en:1;
+               uint64_t reserved_4_15:12;
+               uint64_t phys_bp:16;
+               uint64_t logl_en:16;
+               uint64_t phys_en:16;
+#endif
        } s;
        struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
        struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
+       struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx;
+       struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx;
+       struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1;
+       struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx;
+       struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx;
+       struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1;
+       struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx;
 };
 
 union cvmx_gmxx_prtx_cfg {
        uint64_t u64;
        struct cvmx_gmxx_prtx_cfg_s {
-               uint64_t reserved_14_63:50;
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_22_63:42;
+               uint64_t pknd:6;
+               uint64_t reserved_14_15:2;
                uint64_t tx_idle:1;
                uint64_t rx_idle:1;
                uint64_t reserved_9_11:3;
@@ -413,30 +2600,87 @@ union cvmx_gmxx_prtx_cfg {
                uint64_t duplex:1;
                uint64_t speed:1;
                uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t speed:1;
+               uint64_t duplex:1;
+               uint64_t slottime:1;
+               uint64_t reserved_4_7:4;
+               uint64_t speed_msb:1;
+               uint64_t reserved_9_11:3;
+               uint64_t rx_idle:1;
+               uint64_t tx_idle:1;
+               uint64_t reserved_14_15:2;
+               uint64_t pknd:6;
+               uint64_t reserved_22_63:42;
+#endif
        } s;
        struct cvmx_gmxx_prtx_cfg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t slottime:1;
                uint64_t duplex:1;
                uint64_t speed:1;
                uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t speed:1;
+               uint64_t duplex:1;
+               uint64_t slottime:1;
+               uint64_t reserved_4_63:60;
+#endif
        } cn30xx;
        struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
        struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
        struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
        struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
-       struct cvmx_gmxx_prtx_cfg_s cn52xx;
-       struct cvmx_gmxx_prtx_cfg_s cn52xxp1;
-       struct cvmx_gmxx_prtx_cfg_s cn56xx;
-       struct cvmx_gmxx_prtx_cfg_s cn56xxp1;
+       struct cvmx_gmxx_prtx_cfg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_14_63:50;
+               uint64_t tx_idle:1;
+               uint64_t rx_idle:1;
+               uint64_t reserved_9_11:3;
+               uint64_t speed_msb:1;
+               uint64_t reserved_4_7:4;
+               uint64_t slottime:1;
+               uint64_t duplex:1;
+               uint64_t speed:1;
+               uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t speed:1;
+               uint64_t duplex:1;
+               uint64_t slottime:1;
+               uint64_t reserved_4_7:4;
+               uint64_t speed_msb:1;
+               uint64_t reserved_9_11:3;
+               uint64_t rx_idle:1;
+               uint64_t tx_idle:1;
+               uint64_t reserved_14_63:50;
+#endif
+       } cn52xx;
+       struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1;
+       struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx;
+       struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1;
        struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
        struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
+       struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx;
+       struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx;
+       struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1;
+       struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx;
+       struct cvmx_gmxx_prtx_cfg_s cn68xx;
+       struct cvmx_gmxx_prtx_cfg_s cn68xxp1;
+       struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx;
 };
 
 union cvmx_gmxx_rxx_adr_cam0 {
        uint64_t u64;
        struct cvmx_gmxx_rxx_adr_cam0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t adr:64;
+#else
+               uint64_t adr:64;
+#endif
        } s;
        struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
        struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
@@ -449,12 +2693,23 @@ union cvmx_gmxx_rxx_adr_cam0 {
        struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
        struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
        struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
+       struct cvmx_gmxx_rxx_adr_cam0_s cn61xx;
+       struct cvmx_gmxx_rxx_adr_cam0_s cn63xx;
+       struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1;
+       struct cvmx_gmxx_rxx_adr_cam0_s cn66xx;
+       struct cvmx_gmxx_rxx_adr_cam0_s cn68xx;
+       struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1;
+       struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx;
 };
 
 union cvmx_gmxx_rxx_adr_cam1 {
        uint64_t u64;
        struct cvmx_gmxx_rxx_adr_cam1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t adr:64;
+#else
                uint64_t adr:64;
+#endif
        } s;
        struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
        struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
@@ -467,12 +2722,23 @@ union cvmx_gmxx_rxx_adr_cam1 {
        struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
        struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
        struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
+       struct cvmx_gmxx_rxx_adr_cam1_s cn61xx;
+       struct cvmx_gmxx_rxx_adr_cam1_s cn63xx;
+       struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1;
+       struct cvmx_gmxx_rxx_adr_cam1_s cn66xx;
+       struct cvmx_gmxx_rxx_adr_cam1_s cn68xx;
+       struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1;
+       struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx;
 };
 
 union cvmx_gmxx_rxx_adr_cam2 {
        uint64_t u64;
        struct cvmx_gmxx_rxx_adr_cam2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t adr:64;
+#else
                uint64_t adr:64;
+#endif
        } s;
        struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
        struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
@@ -485,12 +2751,23 @@ union cvmx_gmxx_rxx_adr_cam2 {
        struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
        struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
        struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
+       struct cvmx_gmxx_rxx_adr_cam2_s cn61xx;
+       struct cvmx_gmxx_rxx_adr_cam2_s cn63xx;
+       struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1;
+       struct cvmx_gmxx_rxx_adr_cam2_s cn66xx;
+       struct cvmx_gmxx_rxx_adr_cam2_s cn68xx;
+       struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1;
+       struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx;
 };
 
 union cvmx_gmxx_rxx_adr_cam3 {
        uint64_t u64;
        struct cvmx_gmxx_rxx_adr_cam3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t adr:64;
+#else
                uint64_t adr:64;
+#endif
        } s;
        struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
        struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
@@ -503,12 +2780,23 @@ union cvmx_gmxx_rxx_adr_cam3 {
        struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
        struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
        struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
+       struct cvmx_gmxx_rxx_adr_cam3_s cn61xx;
+       struct cvmx_gmxx_rxx_adr_cam3_s cn63xx;
+       struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1;
+       struct cvmx_gmxx_rxx_adr_cam3_s cn66xx;
+       struct cvmx_gmxx_rxx_adr_cam3_s cn68xx;
+       struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1;
+       struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx;
 };
 
 union cvmx_gmxx_rxx_adr_cam4 {
        uint64_t u64;
        struct cvmx_gmxx_rxx_adr_cam4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t adr:64;
+#else
                uint64_t adr:64;
+#endif
        } s;
        struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
        struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
@@ -521,12 +2809,23 @@ union cvmx_gmxx_rxx_adr_cam4 {
        struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
        struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
        struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
+       struct cvmx_gmxx_rxx_adr_cam4_s cn61xx;
+       struct cvmx_gmxx_rxx_adr_cam4_s cn63xx;
+       struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1;
+       struct cvmx_gmxx_rxx_adr_cam4_s cn66xx;
+       struct cvmx_gmxx_rxx_adr_cam4_s cn68xx;
+       struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1;
+       struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx;
 };
 
 union cvmx_gmxx_rxx_adr_cam5 {
        uint64_t u64;
        struct cvmx_gmxx_rxx_adr_cam5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t adr:64;
+#else
                uint64_t adr:64;
+#endif
        } s;
        struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
        struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
@@ -539,13 +2838,42 @@ union cvmx_gmxx_rxx_adr_cam5 {
        struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
        struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
        struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
+       struct cvmx_gmxx_rxx_adr_cam5_s cn61xx;
+       struct cvmx_gmxx_rxx_adr_cam5_s cn63xx;
+       struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1;
+       struct cvmx_gmxx_rxx_adr_cam5_s cn66xx;
+       struct cvmx_gmxx_rxx_adr_cam5_s cn68xx;
+       struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1;
+       struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx;
+};
+
+union cvmx_gmxx_rxx_adr_cam_all_en {
+       uint64_t u64;
+       struct cvmx_gmxx_rxx_adr_cam_all_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_32_63:32;
+               uint64_t en:32;
+#else
+               uint64_t en:32;
+               uint64_t reserved_32_63:32;
+#endif
+       } s;
+       struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx;
+       struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx;
+       struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx;
+       struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx;
 };
 
 union cvmx_gmxx_rxx_adr_cam_en {
        uint64_t u64;
        struct cvmx_gmxx_rxx_adr_cam_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t en:8;
+#else
+               uint64_t en:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
        struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
@@ -558,15 +2886,29 @@ union cvmx_gmxx_rxx_adr_cam_en {
        struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
        struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
        struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
+       struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx;
+       struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx;
+       struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1;
+       struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx;
+       struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx;
+       struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1;
+       struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx;
 };
 
 union cvmx_gmxx_rxx_adr_ctl {
        uint64_t u64;
        struct cvmx_gmxx_rxx_adr_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t cam_mode:1;
                uint64_t mcst:2;
                uint64_t bcst:1;
+#else
+               uint64_t bcst:1;
+               uint64_t mcst:2;
+               uint64_t cam_mode:1;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
        struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
        struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
@@ -579,13 +2921,25 @@ union cvmx_gmxx_rxx_adr_ctl {
        struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
        struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
        struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
+       struct cvmx_gmxx_rxx_adr_ctl_s cn61xx;
+       struct cvmx_gmxx_rxx_adr_ctl_s cn63xx;
+       struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1;
+       struct cvmx_gmxx_rxx_adr_ctl_s cn66xx;
+       struct cvmx_gmxx_rxx_adr_ctl_s cn68xx;
+       struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1;
+       struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx;
 };
 
 union cvmx_gmxx_rxx_decision {
        uint64_t u64;
        struct cvmx_gmxx_rxx_decision_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t cnt:5;
+#else
+               uint64_t cnt:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_gmxx_rxx_decision_s cn30xx;
        struct cvmx_gmxx_rxx_decision_s cn31xx;
@@ -598,11 +2952,19 @@ union cvmx_gmxx_rxx_decision {
        struct cvmx_gmxx_rxx_decision_s cn56xxp1;
        struct cvmx_gmxx_rxx_decision_s cn58xx;
        struct cvmx_gmxx_rxx_decision_s cn58xxp1;
+       struct cvmx_gmxx_rxx_decision_s cn61xx;
+       struct cvmx_gmxx_rxx_decision_s cn63xx;
+       struct cvmx_gmxx_rxx_decision_s cn63xxp1;
+       struct cvmx_gmxx_rxx_decision_s cn66xx;
+       struct cvmx_gmxx_rxx_decision_s cn68xx;
+       struct cvmx_gmxx_rxx_decision_s cn68xxp1;
+       struct cvmx_gmxx_rxx_decision_s cnf71xx;
 };
 
 union cvmx_gmxx_rxx_frm_chk {
        uint64_t u64;
        struct cvmx_gmxx_rxx_frm_chk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t niberr:1;
                uint64_t skperr:1;
@@ -614,12 +2976,26 @@ union cvmx_gmxx_rxx_frm_chk {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t reserved_10_63:54;
+#endif
        } s;
        struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
        struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
        struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
        struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
        struct cvmx_gmxx_rxx_frm_chk_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t niberr:1;
                uint64_t skperr:1;
@@ -631,8 +3007,22 @@ union cvmx_gmxx_rxx_frm_chk {
                uint64_t reserved_2_2:1;
                uint64_t carext:1;
                uint64_t reserved_0_0:1;
+#else
+               uint64_t reserved_0_0:1;
+               uint64_t carext:1;
+               uint64_t reserved_2_2:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t reserved_6_6:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t reserved_10_63:54;
+#endif
        } cn50xx;
        struct cvmx_gmxx_rxx_frm_chk_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t skperr:1;
                uint64_t rcverr:1;
@@ -642,18 +3032,61 @@ union cvmx_gmxx_rxx_frm_chk {
                uint64_t reserved_2_2:1;
                uint64_t carext:1;
                uint64_t reserved_0_0:1;
+#else
+               uint64_t reserved_0_0:1;
+               uint64_t carext:1;
+               uint64_t reserved_2_2:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t reserved_5_6:2;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_63:55;
+#endif
        } cn52xx;
        struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
        struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
        struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
        struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
        struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
+       struct cvmx_gmxx_rxx_frm_chk_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_9_63:55;
+               uint64_t skperr:1;
+               uint64_t rcverr:1;
+               uint64_t reserved_5_6:2;
+               uint64_t fcserr:1;
+               uint64_t jabber:1;
+               uint64_t reserved_2_2:1;
+               uint64_t carext:1;
+               uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t reserved_2_2:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t reserved_5_6:2;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_63:55;
+#endif
+       } cn61xx;
+       struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx;
+       struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1;
+       struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx;
+       struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx;
+       struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1;
+       struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx;
 };
 
 union cvmx_gmxx_rxx_frm_ctl {
        uint64_t u64;
        struct cvmx_gmxx_rxx_frm_ctl_s {
-               uint64_t reserved_11_63:53;
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_13_63:51;
+               uint64_t ptp_mode:1;
+               uint64_t reserved_11_11:1;
                uint64_t null_dis:1;
                uint64_t pre_align:1;
                uint64_t pad_len:1;
@@ -665,8 +3098,25 @@ union cvmx_gmxx_rxx_frm_ctl {
                uint64_t ctl_drp:1;
                uint64_t pre_strp:1;
                uint64_t pre_chk:1;
+#else
+               uint64_t pre_chk:1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t vlan_len:1;
+               uint64_t pad_len:1;
+               uint64_t pre_align:1;
+               uint64_t null_dis:1;
+               uint64_t reserved_11_11:1;
+               uint64_t ptp_mode:1;
+               uint64_t reserved_13_63:51;
+#endif
        } s;
        struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t pad_len:1;
                uint64_t vlan_len:1;
@@ -677,8 +3127,21 @@ union cvmx_gmxx_rxx_frm_ctl {
                uint64_t ctl_drp:1;
                uint64_t pre_strp:1;
                uint64_t pre_chk:1;
+#else
+               uint64_t pre_chk:1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t vlan_len:1;
+               uint64_t pad_len:1;
+               uint64_t reserved_9_63:55;
+#endif
        } cn30xx;
        struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t vlan_len:1;
                uint64_t pre_free:1;
@@ -688,11 +3151,110 @@ union cvmx_gmxx_rxx_frm_ctl {
                uint64_t ctl_drp:1;
                uint64_t pre_strp:1;
                uint64_t pre_chk:1;
+#else
+               uint64_t pre_chk:1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t vlan_len:1;
+               uint64_t reserved_8_63:56;
+#endif
        } cn31xx;
        struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
        struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
        struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_11_63:53;
+               uint64_t null_dis:1;
+               uint64_t pre_align:1;
+               uint64_t reserved_7_8:2;
+               uint64_t pre_free:1;
+               uint64_t ctl_smac:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_drp:1;
+               uint64_t pre_strp:1;
+               uint64_t pre_chk:1;
+#else
+               uint64_t pre_chk:1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t reserved_7_8:2;
+               uint64_t pre_align:1;
+               uint64_t null_dis:1;
+               uint64_t reserved_11_63:53;
+#endif
+       } cn50xx;
+       struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
+       struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
+       struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
+       struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_10_63:54;
+               uint64_t pre_align:1;
+               uint64_t reserved_7_8:2;
+               uint64_t pre_free:1;
+               uint64_t ctl_smac:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_drp:1;
+               uint64_t pre_strp:1;
+               uint64_t pre_chk:1;
+#else
+               uint64_t pre_chk:1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t reserved_7_8:2;
+               uint64_t pre_align:1;
+               uint64_t reserved_10_63:54;
+#endif
+       } cn56xxp1;
+       struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_11_63:53;
+               uint64_t null_dis:1;
+               uint64_t pre_align:1;
+               uint64_t pad_len:1;
+               uint64_t vlan_len:1;
+               uint64_t pre_free:1;
+               uint64_t ctl_smac:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_drp:1;
+               uint64_t pre_strp:1;
+               uint64_t pre_chk:1;
+#else
+               uint64_t pre_chk:1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t vlan_len:1;
+               uint64_t pad_len:1;
+               uint64_t pre_align:1;
+               uint64_t null_dis:1;
                uint64_t reserved_11_63:53;
+#endif
+       } cn58xx;
+       struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
+       struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_13_63:51;
+               uint64_t ptp_mode:1;
+               uint64_t reserved_11_11:1;
                uint64_t null_dis:1;
                uint64_t pre_align:1;
                uint64_t reserved_7_8:2;
@@ -703,31 +3265,40 @@ union cvmx_gmxx_rxx_frm_ctl {
                uint64_t ctl_drp:1;
                uint64_t pre_strp:1;
                uint64_t pre_chk:1;
-       } cn50xx;
-       struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
-       struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
-       struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
-       struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
-               uint64_t reserved_10_63:54;
-               uint64_t pre_align:1;
-               uint64_t reserved_7_8:2;
-               uint64_t pre_free:1;
-               uint64_t ctl_smac:1;
-               uint64_t ctl_mcst:1;
-               uint64_t ctl_bck:1;
-               uint64_t ctl_drp:1;
-               uint64_t pre_strp:1;
+#else
                uint64_t pre_chk:1;
-       } cn56xxp1;
-       struct cvmx_gmxx_rxx_frm_ctl_s cn58xx;
-       struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t reserved_7_8:2;
+               uint64_t pre_align:1;
+               uint64_t null_dis:1;
+               uint64_t reserved_11_11:1;
+               uint64_t ptp_mode:1;
+               uint64_t reserved_13_63:51;
+#endif
+       } cn61xx;
+       struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx;
+       struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1;
+       struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx;
+       struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx;
+       struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1;
+       struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx;
 };
 
 union cvmx_gmxx_rxx_frm_max {
        uint64_t u64;
        struct cvmx_gmxx_rxx_frm_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t len:16;
+#else
+               uint64_t len:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_gmxx_rxx_frm_max_s cn30xx;
        struct cvmx_gmxx_rxx_frm_max_s cn31xx;
@@ -740,8 +3311,13 @@ union cvmx_gmxx_rxx_frm_max {
 union cvmx_gmxx_rxx_frm_min {
        uint64_t u64;
        struct cvmx_gmxx_rxx_frm_min_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t len:16;
+#else
+               uint64_t len:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_gmxx_rxx_frm_min_s cn30xx;
        struct cvmx_gmxx_rxx_frm_min_s cn31xx;
@@ -754,8 +3330,13 @@ union cvmx_gmxx_rxx_frm_min {
 union cvmx_gmxx_rxx_ifg {
        uint64_t u64;
        struct cvmx_gmxx_rxx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t ifg:4;
+#else
+               uint64_t ifg:4;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
        struct cvmx_gmxx_rxx_ifg_s cn30xx;
        struct cvmx_gmxx_rxx_ifg_s cn31xx;
@@ -768,11 +3349,19 @@ union cvmx_gmxx_rxx_ifg {
        struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
        struct cvmx_gmxx_rxx_ifg_s cn58xx;
        struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
+       struct cvmx_gmxx_rxx_ifg_s cn61xx;
+       struct cvmx_gmxx_rxx_ifg_s cn63xx;
+       struct cvmx_gmxx_rxx_ifg_s cn63xxp1;
+       struct cvmx_gmxx_rxx_ifg_s cn66xx;
+       struct cvmx_gmxx_rxx_ifg_s cn68xx;
+       struct cvmx_gmxx_rxx_ifg_s cn68xxp1;
+       struct cvmx_gmxx_rxx_ifg_s cnf71xx;
 };
 
 union cvmx_gmxx_rxx_int_en {
        uint64_t u64;
        struct cvmx_gmxx_rxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_29_63:35;
                uint64_t hg2cc:1;
                uint64_t hg2fld:1;
@@ -803,8 +3392,41 @@ union cvmx_gmxx_rxx_int_en {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t pause_drp:1;
+               uint64_t loc_fault:1;
+               uint64_t rem_fault:1;
+               uint64_t bad_seq:1;
+               uint64_t bad_term:1;
+               uint64_t unsop:1;
+               uint64_t uneop:1;
+               uint64_t undat:1;
+               uint64_t hg2fld:1;
+               uint64_t hg2cc:1;
+               uint64_t reserved_29_63:35;
+#endif
        } s;
        struct cvmx_gmxx_rxx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_19_63:45;
                uint64_t phy_dupx:1;
                uint64_t phy_spd:1;
@@ -825,11 +3447,34 @@ union cvmx_gmxx_rxx_int_en {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t reserved_19_63:45;
+#endif
        } cn30xx;
        struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
        struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
        struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
        struct cvmx_gmxx_rxx_int_en_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t phy_dupx:1;
@@ -851,8 +3496,32 @@ union cvmx_gmxx_rxx_int_en {
                uint64_t reserved_2_2:1;
                uint64_t carext:1;
                uint64_t reserved_0_0:1;
+#else
+               uint64_t reserved_0_0:1;
+               uint64_t carext:1;
+               uint64_t reserved_2_2:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t reserved_6_6:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } cn50xx;
        struct cvmx_gmxx_rxx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_29_63:35;
                uint64_t hg2cc:1;
                uint64_t hg2fld:1;
@@ -880,10 +3549,40 @@ union cvmx_gmxx_rxx_int_en {
                uint64_t reserved_2_2:1;
                uint64_t carext:1;
                uint64_t reserved_0_0:1;
+#else
+               uint64_t reserved_0_0:1;
+               uint64_t carext:1;
+               uint64_t reserved_2_2:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t reserved_5_6:2;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_9:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t reserved_16_18:3;
+               uint64_t pause_drp:1;
+               uint64_t loc_fault:1;
+               uint64_t rem_fault:1;
+               uint64_t bad_seq:1;
+               uint64_t bad_term:1;
+               uint64_t unsop:1;
+               uint64_t uneop:1;
+               uint64_t undat:1;
+               uint64_t hg2fld:1;
+               uint64_t hg2cc:1;
+               uint64_t reserved_29_63:35;
+#endif
        } cn52xx;
        struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
        struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
        struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_27_63:37;
                uint64_t undat:1;
                uint64_t uneop:1;
@@ -909,8 +3608,36 @@ union cvmx_gmxx_rxx_int_en {
                uint64_t reserved_2_2:1;
                uint64_t carext:1;
                uint64_t reserved_0_0:1;
+#else
+               uint64_t reserved_0_0:1;
+               uint64_t carext:1;
+               uint64_t reserved_2_2:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t reserved_5_6:2;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_9:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t reserved_16_18:3;
+               uint64_t pause_drp:1;
+               uint64_t loc_fault:1;
+               uint64_t rem_fault:1;
+               uint64_t bad_seq:1;
+               uint64_t bad_term:1;
+               uint64_t unsop:1;
+               uint64_t uneop:1;
+               uint64_t undat:1;
+               uint64_t reserved_27_63:37;
+#endif
        } cn56xxp1;
        struct cvmx_gmxx_rxx_int_en_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t phy_dupx:1;
@@ -932,13 +3659,102 @@ union cvmx_gmxx_rxx_int_en {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } cn58xx;
        struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
+       struct cvmx_gmxx_rxx_int_en_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t reserved_29_63:35;
+               uint64_t hg2cc:1;
+               uint64_t hg2fld:1;
+               uint64_t undat:1;
+               uint64_t uneop:1;
+               uint64_t unsop:1;
+               uint64_t bad_term:1;
+               uint64_t bad_seq:1;
+               uint64_t rem_fault:1;
+               uint64_t loc_fault:1;
+               uint64_t pause_drp:1;
+               uint64_t reserved_16_18:3;
+               uint64_t ifgerr:1;
+               uint64_t coldet:1;
+               uint64_t falerr:1;
+               uint64_t rsverr:1;
+               uint64_t pcterr:1;
+               uint64_t ovrerr:1;
+               uint64_t reserved_9_9:1;
+               uint64_t skperr:1;
+               uint64_t rcverr:1;
+               uint64_t reserved_5_6:2;
+               uint64_t fcserr:1;
+               uint64_t jabber:1;
+               uint64_t reserved_2_2:1;
+               uint64_t carext:1;
+               uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t reserved_2_2:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t reserved_5_6:2;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_9:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t reserved_16_18:3;
+               uint64_t pause_drp:1;
+               uint64_t loc_fault:1;
+               uint64_t rem_fault:1;
+               uint64_t bad_seq:1;
+               uint64_t bad_term:1;
+               uint64_t unsop:1;
+               uint64_t uneop:1;
+               uint64_t undat:1;
+               uint64_t hg2fld:1;
+               uint64_t hg2cc:1;
+               uint64_t reserved_29_63:35;
+#endif
+       } cn61xx;
+       struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx;
+       struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1;
+       struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx;
+       struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx;
+       struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1;
+       struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx;
 };
 
 union cvmx_gmxx_rxx_int_reg {
        uint64_t u64;
        struct cvmx_gmxx_rxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_29_63:35;
                uint64_t hg2cc:1;
                uint64_t hg2fld:1;
@@ -969,8 +3785,41 @@ union cvmx_gmxx_rxx_int_reg {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t pause_drp:1;
+               uint64_t loc_fault:1;
+               uint64_t rem_fault:1;
+               uint64_t bad_seq:1;
+               uint64_t bad_term:1;
+               uint64_t unsop:1;
+               uint64_t uneop:1;
+               uint64_t undat:1;
+               uint64_t hg2fld:1;
+               uint64_t hg2cc:1;
+               uint64_t reserved_29_63:35;
+#endif
        } s;
        struct cvmx_gmxx_rxx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_19_63:45;
                uint64_t phy_dupx:1;
                uint64_t phy_spd:1;
@@ -991,11 +3840,34 @@ union cvmx_gmxx_rxx_int_reg {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t reserved_19_63:45;
+#endif
        } cn30xx;
        struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
        struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
        struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
        struct cvmx_gmxx_rxx_int_reg_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t phy_dupx:1;
@@ -1017,8 +3889,32 @@ union cvmx_gmxx_rxx_int_reg {
                uint64_t reserved_2_2:1;
                uint64_t carext:1;
                uint64_t reserved_0_0:1;
+#else
+               uint64_t reserved_0_0:1;
+               uint64_t carext:1;
+               uint64_t reserved_2_2:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t reserved_6_6:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } cn50xx;
        struct cvmx_gmxx_rxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_29_63:35;
                uint64_t hg2cc:1;
                uint64_t hg2fld:1;
@@ -1046,10 +3942,40 @@ union cvmx_gmxx_rxx_int_reg {
                uint64_t reserve