[PATCH 5/8] MIPS: OCTEON: Add OCTEON_IRQ_* definitions for cn68XX chips.

[David Daney <ddaney.cavm@gmail.com>]

From: David Daney <david.daney@cavium.com>

There are 64 workqueue, 32 watchdog, and 4 mbox.

Signed-off-by: David Daney <david.daney@cavium.com>
---
 arch/mips/include/asm/mach-cavium-octeon/irq.h |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h 
b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 16b7da3..38b25d4 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -21,10 +21,11 @@ enum octeon_irq {
        OCTEON_IRQ_TIMER,
 /* sources in CIU_INTX_EN0 */
        OCTEON_IRQ_WORKQ0,
-       OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16,
-       OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
-       OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
+       OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64,
+       OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32,
        OCTEON_IRQ_MBOX1,
+       OCTEON_IRQ_MBOX2,
+       OCTEON_IRQ_MBOX3,
        OCTEON_IRQ_PCI_INT0,
        OCTEON_IRQ_PCI_INT1,
        OCTEON_IRQ_PCI_INT2,
-- 
1.7.2.3