| To: | Kevin Cernekee <cernekee@gmail.com> |
|---|---|
| Subject: | Re: [PATCH] Revert "MIPS: cache: Provide cache flush operations for XFS" |
| From: | Leonid Yegoshin <yegoshin@mips.com> |
| Date: | Tue, 10 Apr 2012 11:03:35 -0700 |
| Cc: | "Steven J. Hill" <sjhill@mips.com>, <linux-mips@linux-mips.org>, <ralf@linux-mips.org> |
| In-reply-to: | <CAJiQ=7AjtSB8KQ9+edUOvW+70nAWzh6c8B26ehnEpuud6QeMJA@mail.gmail.com> |
| References: | <1333987989-1178-1-git-send-email-sjhill@mips.com> <CAJiQ=7AjtSB8KQ9+edUOvW+70nAWzh6c8B26ehnEpuud6QeMJA@mail.gmail.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.18) Gecko/20110617 Thunderbird/3.1.11 |
On 04/09/2012 07:44 PM, Kevin Cernekee wrote: On Mon,Is there a reason why Ralf's original approach was not workable? It doesn't work with HIGHMEM + cache aliasing. It also uses cache flush (blast_dcache) to buffer instead of cache invalidate after read I/O is completed. I suspect that reimplementing the *_kernel_vmap_range functions using _dma_cache_* would result in a double L2 flush on the same memory regions on systems with cache aliases, and an unnecessary L1+L2 flush on systems without aliases. Good point. I put that to set it working. Now, after your comment, I think it has sense to try with L1 only. - Leonid. |
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: [PATCH 4/5] staging: octeon_ethernet: Convert to use device tree., Greg Kroah-Hartman |
|---|---|
| Next by Date: | Re: [PATCH] Add MIPS64R2 core support., Leonid Yegoshin |
| Previous by Thread: | Re: [PATCH] Revert "MIPS: cache: Provide cache flush operations for XFS", Kevin Cernekee |
| Next by Thread: | [PATCH] Revert fixrange_init() limiting to the FIXMAP region., Steven J. Hill |
| Indexes: | [Date] [Thread] [Top] [All Lists] |