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Re: [PATCH 1/5] MIPS: Add support for the 1074K core.

To: "Steven J. Hill" <sjhill@mips.com>
Subject: Re: [PATCH 1/5] MIPS: Add support for the 1074K core.
From: Jonas Gorski <jonas.gorski@gmail.com>
Date: Sat, 7 Apr 2012 12:47:27 +0200
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, sjhill@realitydiluted.com
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Hi,

On 6 April 2012 19:57, Steven J. Hill <sjhill@mips.com> wrote:
> From: "Steven J. Hill" <sjhill@mips.com>
>
> This patch adds support for detecting and using 1074K cores.
> Signed-off-by: Steven J. Hill <sjhill@mips.com>
>
> (snip)
>
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index bda8eb2..a08e75d 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void)
>                        c->icache.linesz = 2 << lsize;
>                else
>                        c->icache.linesz = lsize;
> -               c->icache.sets = 64 << ((config1 >> 22) & 7);
> +               c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);

Why this change? According to the 1074K datasheet it is still 64 *
2^S, so to me it looks like the previous version was correct. Also
adding first and then masking looks really wrong, and will produce
wrong results for 0x7.

>                c->icache.ways = 1 + ((config1 >> 16) & 7);
>
>                icache_size = c->icache.sets *
> @@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void)
>                        c->dcache.linesz = 2 << lsize;
>                else
>                        c->dcache.linesz= lsize;
> -               c->dcache.sets = 64 << ((config1 >> 13) & 7);
> +               c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);

See above.

>                c->dcache.ways = 1 + ((config1 >> 7) & 7);
>
>                dcache_size = c->dcache.sets *
> (snip)


Jonas

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