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[PATCH 4/5] MIPS: Malta PCI changes for PCI 2.1 compatibility and confli

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH 4/5] MIPS: Malta PCI changes for PCI 2.1 compatibility and conflicts.
From: "Steven J. Hill" <sjhill@mips.com>
Date: Fri, 6 Apr 2012 12:59:43 -0500
Cc: "Steven J. Hill" <sjhill@mips.com>, sjhill@realitydiluted.com
Sender: linux-mips-bounce@linux-mips.org
From: "Steven J. Hill" <sjhill@mips.com>

Turns on PCI 2.1 compatibility for the Malta platform for the
PIIX4 controller. Change start address to avoid conflicts with
the ACPI and SMB devices.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
 arch/mips/mti-malta/malta-pci.c   |    5 +++--
 arch/mips/mti-malta/malta-setup.c |   11 +++++++++++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
index bf80921..afeb619 100644
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/mti-malta/malta-pci.c
@@ -241,8 +241,9 @@ void __init mips_pcibios_init(void)
                return;
        }
 
-       if (controller->io_resource->start < 0x00001000UL)      /* FIXME */
-               controller->io_resource->start = 0x00001000UL;
+       /* Change start address to avoid conflicts with ACPI and SMB devices */
+       if (controller->io_resource->start < 0x00002000UL)      /* FIXME */
+               controller->io_resource->start = 0x00002000UL;
 
        iomem_resource.end &= 0xfffffffffULL;                   /* 64 GB */
        ioport_resource.end = controller->io_resource->end;
diff --git a/arch/mips/mti-malta/malta-setup.c 
b/arch/mips/mti-malta/malta-setup.c
index b7f37d4..5f7d113 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -222,3 +222,14 @@ void __init plat_mem_setup(void)
        board_be_init = malta_be_init;
        board_be_handler = malta_be_handler;
 }
+/* Enable PCI 2.1 compatibility in PIIX4 */
+static void __init quirk_dlcsetup(struct pci_dev *dev)
+{
+       u8 odlc, ndlc;
+       (void) pci_read_config_byte(dev, 0x82, &odlc);
+       /* Enable passive releases and delayed transaction */
+       ndlc = odlc | 7;
+       (void) pci_write_config_byte(dev, 0x82, ndlc);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
+               quirk_dlcsetup);
-- 
1.7.9.6


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