Our FP emulator is hardcoded for the MIPS IV FP instruction set and does
not match the FP ISA with the general ISA. However for the few MIPS IV FP
instructions that use the COP1X major opcode it relies on the Coprocessor
Unusable exception to be delivered as a COP1 rather than COP3 exception.
This includes indexed transfer (LDXC1, etc.) and FP multiply-accumulate
(MADD.D, etc.) instructions.
All the MIPS I and MIPS II processors and some newer chips that do not
implement the FPU use the COP3 exception however. Therefore I believe the
kernel should follow and redirect any COP3 Unusable traps to the emulator
unless an actual FPU part or core is present.
This is a change that implements it. Any minor opcode encodings that are
not recognised as valid FP instructions are rejected by the emulator and
will result in a SIGILL signal being delivered as they currently do. We
do not support vendor-specific coprocessor 3 implementations supported
with MIPS I and MIPS II ISA processors; we never set CP0.Status.CU3.
If matching between the CPU and the FPU ISA is considered required one
day, this can still be done in the emulator itself. I think the CpU
exception dispatcher is not the right place to do this anyway, as there
are further differences between MIPS I, MIPS II, MIPS III, MIPS IV and
MIPS32 FP ISAs.
Corresponding explanation of this implementation is included within the
Signed-off-by: Maciej W. Rozycki <email@example.com>
Any progress with this change?
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index c6fc6a0..b86eb3d 100644
@@ -1066,6 +1066,24 @@ asmlinkage void do_cpu(struct pt_regs *regs)
+ case 3:
+ * Old (MIPS I and MIPS II) processors will set this code
+ * for COP1X opcode instructions that replaced the original
+ * COP3 space. We don't limit COP1 space instructions in
+ * the emulator according to the CPU ISA, so we want to
+ * treat COP1X instructions consistently regardless of which
+ * code the CPU chose. Therefore we redirect this trap to
+ * the FP emulator too.
+ * Then some newer FPU-less processors use this code
+ * erroneously too, so they are covered by this choice
+ * as well.
+ if (raw_cpu_has_fpu)
+ /* Fall through. */
if (used_math()) /* Using the FPU again. */
@@ -1089,9 +1107,6 @@ asmlinkage void do_cpu(struct pt_regs *regs)
raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
- case 3: