On Mon, Feb 20, 2012 at 10:34:20AM +0100, Mikael Starvik wrote:
> I'm running Linux 3.2 on a MIPS 34K with two VPEs (in MT_SMP configuration).
> It works fine in UP but with SMP it deadlocks during bootup (both CPUs gets
> idle). Typically like this:
> [ 0.090000] CPU revision is: 01019550 (MIPS 34Kc)
> [ 0.090000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [ 0.090000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32
> [ 0.170000] Brought up 2 CPUs
> <No more output>
> I have tried to enable __ARCH_WANT_INTERRUPTS_ON_CTXSW but that didn't
> improve anything. Anyone else got this running or have any thoughts about
> what the problem may be?
It used to work ... Are you testing this on Malta? In my experience if a
CPU hangs at this stage it often is because it does not receive a timer
tick, so all changes to the timer code are candidates to be reviewed.
Git bisect may be the way of least resistance here.