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[PATCH 2/7] bcma: add constants for PCI and use them

To: linville@tuxdriver.com
Subject: [PATCH 2/7] bcma: add constants for PCI and use them
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Tue, 31 Jan 2012 00:03:32 +0100
Cc: zajec5@gmail.com, b43-dev@lists.infradead.org, linux-mips@linux-mips.org, linux-wireless@vger.kernel.org, Hauke Mehrtens <hauke@hauke-m.de>
In-reply-to: <1327964617-7910-1-git-send-email-hauke@hauke-m.de>
References: <1327964617-7910-1-git-send-email-hauke@hauke-m.de>
Sender: linux-mips-bounce@linux-mips.org
There are many magic numbers used in the PCIe code. Replace them with
some constants from the Broadcom SDK and also use them in the pcie host
controller.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 drivers/bcma/driver_pci.c            |  124 +++++++++++++++++++---------------
 include/linux/bcma/bcma_driver_pci.h |   85 +++++++++++++++++++++++
 2 files changed, 155 insertions(+), 54 deletions(-)

diff --git a/drivers/bcma/driver_pci.c b/drivers/bcma/driver_pci.c
index 4fde625..970a38e 100644
--- a/drivers/bcma/driver_pci.c
+++ b/drivers/bcma/driver_pci.c
@@ -4,6 +4,7 @@
  *
  * Copyright 2005, Broadcom Corporation
  * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
  *
  * Licensed under the GNU/GPL. See COPYING for details.
  */
@@ -18,38 +19,39 @@
 
 static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
 {
-       pcicore_write32(pc, 0x130, address);
-       pcicore_read32(pc, 0x130);
-       return pcicore_read32(pc, 0x134);
+       pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
+       pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
+       return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
 }
 
 #if 0
 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
 {
-       pcicore_write32(pc, 0x130, address);
-       pcicore_read32(pc, 0x130);
-       pcicore_write32(pc, 0x134, data);
+       pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
+       pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
+       pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
 }
 #endif
 
 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
 {
-       const u16 mdio_control = 0x128;
-       const u16 mdio_data = 0x12C;
        u32 v;
        int i;
 
-       v = (1 << 30); /* Start of Transaction */
-       v |= (1 << 28); /* Write Transaction */
-       v |= (1 << 17); /* Turnaround */
-       v |= (0x1F << 18);
+       v = BCMA_CORE_PCI_MDIODATA_START;
+       v |= BCMA_CORE_PCI_MDIODATA_WRITE;
+       v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
+             BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
+       v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
+             BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
+       v |= BCMA_CORE_PCI_MDIODATA_TA;
        v |= (phy << 4);
-       pcicore_write32(pc, mdio_data, v);
+       pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
 
        udelay(10);
        for (i = 0; i < 200; i++) {
-               v = pcicore_read32(pc, mdio_control);
-               if (v & 0x100 /* Trans complete */)
+               v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
+               if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
                        break;
                msleep(1);
        }
@@ -57,79 +59,84 @@ static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, 
u8 phy)
 
 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
 {
-       const u16 mdio_control = 0x128;
-       const u16 mdio_data = 0x12C;
        int max_retries = 10;
        u16 ret = 0;
        u32 v;
        int i;
 
-       v = 0x80; /* Enable Preamble Sequence */
-       v |= 0x2; /* MDIO Clock Divisor */
-       pcicore_write32(pc, mdio_control, v);
+       /* enable mdio access to SERDES */
+       v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
+       v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
+       pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
 
        if (pc->core->id.rev >= 10) {
                max_retries = 200;
                bcma_pcie_mdio_set_phy(pc, device);
+               v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
+                    BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
+               v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
+       } else {
+               v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
+               v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
        }
 
-       v = (1 << 30); /* Start of Transaction */
-       v |= (1 << 29); /* Read Transaction */
-       v |= (1 << 17); /* Turnaround */
-       if (pc->core->id.rev < 10)
-               v |= (u32)device << 22;
-       v |= (u32)address << 18;
-       pcicore_write32(pc, mdio_data, v);
+       v = BCMA_CORE_PCI_MDIODATA_START;
+       v |= BCMA_CORE_PCI_MDIODATA_READ;
+       v |= BCMA_CORE_PCI_MDIODATA_TA;
+
+       pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
        /* Wait for the device to complete the transaction */
        udelay(10);
        for (i = 0; i < max_retries; i++) {
-               v = pcicore_read32(pc, mdio_control);
-               if (v & 0x100 /* Trans complete */) {
+               v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
+               if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
                        udelay(10);
-                       ret = pcicore_read32(pc, mdio_data);
+                       ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
                        break;
                }
                msleep(1);
        }
-       pcicore_write32(pc, mdio_control, 0);
+       pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
        return ret;
 }
 
 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
                                u8 address, u16 data)
 {
-       const u16 mdio_control = 0x128;
-       const u16 mdio_data = 0x12C;
        int max_retries = 10;
        u32 v;
        int i;
 
-       v = 0x80; /* Enable Preamble Sequence */
-       v |= 0x2; /* MDIO Clock Divisor */
-       pcicore_write32(pc, mdio_control, v);
+       /* enable mdio access to SERDES */
+       v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
+       v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
+       pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
 
        if (pc->core->id.rev >= 10) {
                max_retries = 200;
                bcma_pcie_mdio_set_phy(pc, device);
+               v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
+                    BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
+               v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
+       } else {
+               v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
+               v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
        }
 
-       v = (1 << 30); /* Start of Transaction */
-       v |= (1 << 28); /* Write Transaction */
-       v |= (1 << 17); /* Turnaround */
-       if (pc->core->id.rev < 10)
-               v |= (u32)device << 22;
-       v |= (u32)address << 18;
+       v = BCMA_CORE_PCI_MDIODATA_START;
+       v |= BCMA_CORE_PCI_MDIODATA_WRITE;
+       v |= BCMA_CORE_PCI_MDIODATA_TA;
        v |= data;
-       pcicore_write32(pc, mdio_data, v);
+       pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
        /* Wait for the device to complete the transaction */
        udelay(10);
        for (i = 0; i < max_retries; i++) {
-               v = pcicore_read32(pc, mdio_control);
-               if (v & 0x100 /* Trans complete */)
+               v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
+               if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
                        break;
                msleep(1);
        }
-       pcicore_write32(pc, mdio_control, 0);
+       pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
 }
 
 /**************************************************
@@ -138,20 +145,29 @@ static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, 
u8 device,
 
 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
 {
-       return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
+       u32 tmp;
+       
+       tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
+       if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
+               return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
+                      BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
+       else
+               return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
 }
 
 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
 {
-       const u8 serdes_pll_device = 0x1D;
-       const u8 serdes_rx_device = 0x1F;
        u16 tmp;
 
-       bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
-                             bcma_pcicore_polarity_workaround(pc));
-       tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
-       if (tmp & 0x4000)
-               bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
+       bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
+                            BCMA_CORE_PCI_SERDES_RX_CTRL,
+                            bcma_pcicore_polarity_workaround(pc));
+       tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
+                                 BCMA_CORE_PCI_SERDES_PLL_CTRL);
+       if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
+               bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
+                                    BCMA_CORE_PCI_SERDES_PLL_CTRL,
+                                    tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
 }
 
 /**************************************************
diff --git a/include/linux/bcma/bcma_driver_pci.h 
b/include/linux/bcma/bcma_driver_pci.h
index 3871b66..67ea7be 100644
--- a/include/linux/bcma/bcma_driver_pci.h
+++ b/include/linux/bcma/bcma_driver_pci.h
@@ -53,6 +53,35 @@ struct pci_dev;
 #define  BCMA_CORE_PCI_SBTOPCI1_MASK           0xFC000000
 #define BCMA_CORE_PCI_SBTOPCI2                 0x0108  /* Backplane to PCI 
translation 2 (sbtopci2) */
 #define  BCMA_CORE_PCI_SBTOPCI2_MASK           0xC0000000
+#define BCMA_CORE_PCI_CONFIG_ADDR              0x0120  /* pcie config space 
access */
+#define BCMA_CORE_PCI_CONFIG_DATA              0x0124  /* pcie config space 
access */
+#define BCMA_CORE_PCI_MDIO_CONTROL             0x0128  /* controls the mdio 
access */
+#define  BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK    0x7f    /* clock to be used on 
MDIO */
+#define  BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL     0x2
+#define  BCMA_CORE_PCI_MDIOCTL_PREAM_EN                0x80    /* Enable 
preamble sequnce */
+#define  BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE     0x100   /* Tranaction complete 
*/
+#define BCMA_CORE_PCI_MDIO_DATA                        0x012c  /* Data to the 
mdio access */
+#define  BCMA_CORE_PCI_MDIODATA_MASK           0x0000ffff /* data 2 bytes */
+#define  BCMA_CORE_PCI_MDIODATA_TA             0x00020000 /* Turnaround */
+#define  BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD        18      /* Regaddr 
shift (rev < 10) */
+#define  BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD       0x003c0000 /* Regaddr 
Mask (rev < 10) */
+#define  BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD        22      /* Physmedia 
devaddr shift (rev < 10) */
+#define  BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD       0x0fc00000 /* Physmedia 
devaddr Mask (rev < 10) */
+#define  BCMA_CORE_PCI_MDIODATA_REGADDR_SHF    18      /* Regaddr shift */
+#define  BCMA_CORE_PCI_MDIODATA_REGADDR_MASK   0x007c0000 /* Regaddr Mask */
+#define  BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF    23      /* Physmedia devaddr 
shift */
+#define  BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK   0x0f800000 /* Physmedia devaddr 
Mask */
+#define  BCMA_CORE_PCI_MDIODATA_WRITE          0x10000000 /* write Transaction 
*/
+#define  BCMA_CORE_PCI_MDIODATA_READ           0x20000000 /* Read Transaction 
*/
+#define  BCMA_CORE_PCI_MDIODATA_START          0x40000000 /* start of 
Transaction */
+#define  BCMA_CORE_PCI_MDIODATA_DEV_ADDR       0x0     /* dev address for 
serdes */
+#define  BCMA_CORE_PCI_MDIODATA_BLK_ADDR       0x1F    /* blk address for 
serdes */
+#define  BCMA_CORE_PCI_MDIODATA_DEV_PLL                0x1d    /* SERDES PLL 
Dev */
+#define  BCMA_CORE_PCI_MDIODATA_DEV_TX         0x1e    /* SERDES TX Dev */
+#define  BCMA_CORE_PCI_MDIODATA_DEV_RX         0x1f    /* SERDES RX Dev */
+#define BCMA_CORE_PCI_PCIEIND_ADDR             0x0130  /* indirect access to 
the internal register */
+#define BCMA_CORE_PCI_PCIEIND_DATA             0x0134  /* Data to/from the 
internal regsiter */
+#define BCMA_CORE_PCI_CLKREQENCTRL             0x0138  /*  >= rev 6, Clkreq 
rdma control */
 #define BCMA_CORE_PCI_PCICFG0                  0x0400  /* PCI config space 0 
(rev >= 8) */
 #define BCMA_CORE_PCI_PCICFG1                  0x0500  /* PCI config space 1 
(rev >= 8) */
 #define BCMA_CORE_PCI_PCICFG2                  0x0600  /* PCI config space 2 
(rev >= 8) */
@@ -72,6 +101,62 @@ struct pci_dev;
 #define  BCMA_CORE_PCI_SBTOPCI_RC_READL                0x00000010 /* Memory 
read line */
 #define  BCMA_CORE_PCI_SBTOPCI_RC_READM                0x00000020 /* Memory 
read multiple */
 
+/* PCIE protocol PHY diagnostic registers */
+#define BCMA_CORE_PCI_PLP_MODEREG              0x200   /* Mode */
+#define BCMA_CORE_PCI_PLP_STATUSREG            0x204   /* Status */
+#define  BCMA_CORE_PCI_PLP_POLARITYINV_STAT    0x10    /* Status reg 
PCIE_PLP_STATUSREG */
+#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG         0x208   /* LTSSM control */
+#define BCMA_CORE_PCI_PLP_LTLINKNUMREG         0x20c   /* Link Training Link 
number */
+#define BCMA_CORE_PCI_PLP_LTLANENUMREG         0x210   /* Link Training Lane 
number */
+#define BCMA_CORE_PCI_PLP_LTNFTSREG            0x214   /* Link Training N_FTS 
*/
+#define BCMA_CORE_PCI_PLP_ATTNREG              0x218   /* Attention */
+#define BCMA_CORE_PCI_PLP_ATTNMASKREG          0x21C   /* Attention Mask */
+#define BCMA_CORE_PCI_PLP_RXERRCTR             0x220   /* Rx Error */
+#define BCMA_CORE_PCI_PLP_RXFRMERRCTR          0x224   /* Rx Framing Error */
+#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG       0x228   /* Rx Error threshold */
+#define BCMA_CORE_PCI_PLP_TESTCTRLREG          0x22C   /* Test Control reg */
+#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG    0x230   /* SERDES Control 
Override */
+#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG                0x234   /* Timing param 
override */
+#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG                0x238   /* RXTX State 
Machine Diag */
+#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG         0x23C   /* LTSSM State Machine 
Diag */
+
+/* PCIE protocol DLLP diagnostic registers */
+#define BCMA_CORE_PCI_DLLP_LCREG               0x100   /* Link Control */
+#define BCMA_CORE_PCI_DLLP_LSREG               0x104   /* Link Status */
+#define BCMA_CORE_PCI_DLLP_LAREG               0x108   /* Link Attention */
+#define  BCMA_CORE_PCI_DLLP_LSREG_LINKUP       (1 << 16)
+#define BCMA_CORE_PCI_DLLP_LAMASKREG           0x10C   /* Link Attention Mask 
*/
+#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG     0x110   /* Next Tx Seq Num */
+#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG    0x114   /* Acked Tx Seq Num */
+#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG   0x118   /* Purged Tx Seq Num */
+#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG         0x11C   /* Rx Sequence Number */
+#define BCMA_CORE_PCI_DLLP_LRREG               0x120   /* Link Replay */
+#define BCMA_CORE_PCI_DLLP_LACKTOREG           0x124   /* Link Ack Timeout */
+#define BCMA_CORE_PCI_DLLP_PMTHRESHREG         0x128   /* Power Management 
Threshold */
+#define BCMA_CORE_PCI_DLLP_RTRYWPREG           0x12C   /* Retry buffer write 
ptr */
+#define BCMA_CORE_PCI_DLLP_RTRYRPREG           0x130   /* Retry buffer Read 
ptr */
+#define BCMA_CORE_PCI_DLLP_RTRYPPREG           0x134   /* Retry buffer Purged 
ptr */
+#define BCMA_CORE_PCI_DLLP_RTRRWREG            0x138   /* Retry buffer 
Read/Write */
+#define BCMA_CORE_PCI_DLLP_ECTHRESHREG         0x13C   /* Error Count 
Threshold */
+#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG                0x140   /* TLP Error 
Counter */
+#define BCMA_CORE_PCI_DLLP_ERRCTRREG           0x144   /* Error Counter */
+#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG         0x148   /* NAK Received Counter 
*/
+#define BCMA_CORE_PCI_DLLP_TESTREG             0x14C   /* Test */
+#define BCMA_CORE_PCI_DLLP_PKTBIST             0x150   /* Packet BIST */
+#define BCMA_CORE_PCI_DLLP_PCIE11              0x154   /* DLLP PCIE 1.1 reg */
+
+/* SERDES RX registers */
+#define BCMA_CORE_PCI_SERDES_RX_CTRL           1       /* Rx cntrl */
+#define  BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE    0x80    /* rxpolarity_force */
+#define  BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40    /* rxpolarity_value */
+#define BCMA_CORE_PCI_SERDES_RX_TIMER1         2       /* Rx Timer1 */
+#define BCMA_CORE_PCI_SERDES_RX_CDR            6       /* CDR */
+#define BCMA_CORE_PCI_SERDES_RX_CDRBW          7       /* CDR BW */
+
+/* SERDES PLL registers */
+#define BCMA_CORE_PCI_SERDES_PLL_CTRL          1       /* PLL control reg */
+#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN      0x4000  /* bit 14 is FREQDET on 
*/
+
 /* PCIcore specific boardflags */
 #define BCMA_CORE_PCI_BFL_NOPCI                        0x00000400 /* Board 
leaves PCI floating */
 
-- 
1.7.5.4


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