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Re: [PATCH] MIPS: Octeon: Don't increase PCIe payload sizes.

To: David Daney <ddaney.cavm@gmail.com>
Subject: Re: [PATCH] MIPS: Octeon: Don't increase PCIe payload sizes.
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 8 Dec 2011 12:35:09 +0000
Cc: linux-mips@linux-mips.org, David Daney <david.daney@cavium.com>
In-reply-to: <1322761877-30221-1-git-send-email-ddaney.cavm@gmail.com>
References: <1322761877-30221-1-git-send-email-ddaney.cavm@gmail.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.21 (2010-09-15)
On Thu, Dec 01, 2011 at 09:51:17AM -0800, David Daney wrote:

> The existing code breaks devices that are capable of large PCIe
> transfers (Silicon Image SATA controllers for example).  We don't have
> code to properly determine the maximum payload size on a per-bus
> basis, so the easiest thing to do is just have all devices use the
> default (128).

Folded into 53ba9ae0 [MIPS: Octeon: Update PCI Latency timer, PCIe payload,
and PCIe max read to allow larger transactions].

Thanks,

  Ralf

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