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[PATCH 3/3 v3] MIPS: introduce CPU_R4K_CACHE_TLB

To: ralf@linux-mips.org
Subject: [PATCH 3/3 v3] MIPS: introduce CPU_R4K_CACHE_TLB
From: Florian Fainelli <florian@openwrt.org>
Date: Tue, 22 Nov 2011 14:59:50 +0100
Cc: linux-mips@linux-mips.org, Florian Fainelli <florian@openwrt.org>
In-reply-to: <1321970390-10887-1-git-send-email-florian@openwrt.org>
References: <1321970390-10887-1-git-send-email-florian@openwrt.org>
Sender: linux-mips-bounce@linux-mips.org
R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
Changes since v2:
- rebased against mips-for-linux-next (remove XLP)

Changes since v1:
- removed CPU_XLR already covered by CPU_R4K_CACHE_TLB
- add back CPU_R8000 to Kconfig exception list and Makefile

 arch/mips/Kconfig     |    4 ++++
 arch/mips/mm/Makefile |   17 +----------------
 2 files changed, 5 insertions(+), 16 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index be02f74..5819325 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1844,6 +1844,10 @@ config CPU_R4K_FPU
        bool
        default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || 
CPU_CAVIUM_OCTEON)
 
+config CPU_R4K_CACHE_TLB
+       bool
+       default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || 
CPU_CAVIUM_OCTEON)
+
 choice
        prompt "MIPS MT options"
 
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 4aa2028..29ca3df 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -11,27 +11,12 @@ obj-$(CONFIG_64BIT)         += pgtable-64.o
 obj-$(CONFIG_HIGHMEM)          += highmem.o
 obj-$(CONFIG_HUGETLB_PAGE)     += hugetlbpage.o
 
-obj-$(CONFIG_CPU_LOONGSON2)    += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_MIPS32)       += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_MIPS64)       += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_NEVADA)       += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_R10000)       += c-r4k.o cex-gen.o tlb-r4k.o
+obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_R3000)                += c-r3k.o tlb-r3k.o
-obj-$(CONFIG_CPU_R4300)                += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_R4X00)                += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_R5000)                += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_R5432)                += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_R5500)                += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_R8000)                += c-r4k.o cex-gen.o tlb-r8k.o
-obj-$(CONFIG_CPU_RM7000)       += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_RM9000)       += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_SB1)          += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
 obj-$(CONFIG_CPU_TX39XX)       += c-tx39.o tlb-r3k.o
-obj-$(CONFIG_CPU_TX49XX)       += c-r4k.o cex-gen.o tlb-r4k.o
-obj-$(CONFIG_CPU_VR41XX)       += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON)        += c-octeon.o cex-oct.o tlb-r4k.o
-obj-$(CONFIG_CPU_XLR)          += c-r4k.o tlb-r4k.o cex-gen.o
-obj-$(CONFIG_CPU_XLP)          += c-r4k.o tlb-r4k.o cex-gen.o
 
 obj-$(CONFIG_IP22_CPU_SCACHE)  += sc-ip22.o
 obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
-- 
1.7.5.4


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