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Re: [PATCH v2 01/11] MIPS: BCM63XX: set default pci cache line size.

To: Maxime Bizon <mbizon@freebox.fr>
Subject: Re: [PATCH v2 01/11] MIPS: BCM63XX: set default pci cache line size.
From: Ralf Baechle <ralf@linux-mips.org>
Date: Fri, 18 Nov 2011 18:28:34 +0000
Cc: linux-mips@linux-mips.org
In-reply-to: <1321639936.32730.33.camel@sakura.staff.proxad.net>
References: <1320430175-13725-1-git-send-email-mbizon@freebox.fr> <1320430175-13725-2-git-send-email-mbizon@freebox.fr> <20111115195438.GF26141@linux-mips.org> <1321639936.32730.33.camel@sakura.staff.proxad.net>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.21 (2010-09-15)
On Fri, Nov 18, 2011 at 07:12:16PM +0100, Maxime Bizon wrote:

> > 
> > Presumably because the CPU cache line size is 16 bytes?  On MIPS we
> > don't set pci_dfl_cache_line_size; a patch (only compile tested) to
> > pick a sane default is below.
> > 
> > Does this work for you? 
> 
> [    0.192000] PCI: CLS 0 bytes, default 16
> 
> yes it does

Excellent, thanks for testing.  So I also queued this one for 3.3.

  Ralf

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