| To: | Ralf Baechle <ralf@linux-mips.org> |
|---|---|
| Subject: | [PATCH] MIPS: Flush huge TLB |
| From: | Hillf Danton <dhillf@gmail.com> |
| Date: | Fri, 18 Nov 2011 21:15:39 +0800 |
| Cc: | David Daney <david.daney@cavium.com>, "Jayachandran C." <jayachandranc@netlogicmicro.com>, linux-mips@linux-mips.org |
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| Sender: | linux-mips-bounce@linux-mips.org |
When flushing TLB, if @vma is backed by huge page, we could flush huge TLB,
due to that huge page is defined to be far from normal page.
Signed-off-by: Hillf Danton <dhillf@gmail.com>
---
--- a/arch/mips/mm/tlb-r4k.c Mon May 30 21:17:04 2011
+++ b/arch/mips/mm/tlb-r4k.c Fri Nov 18 21:13:13 2011
@@ -120,22 +120,30 @@ void local_flush_tlb_range(struct vm_are
if (cpu_context(cpu, mm) != 0) {
unsigned long size, flags;
+ int huge = is_vm_hugetlb_page(vma);
ENTER_CRITICAL(flags);
- size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- size = (size + 1) >> 1;
+ if (huge) {
+ start = round_down(start, HPAGE_SIZE);
+ end = round_up(end, HPAGE_SIZE);
+ size = (end - start) >> HPAGE_SHIFT;
+ } else {
+ start = round_down(start, PAGE_SIZE << 1);
+ end = round_up(end, PAGE_SIZE << 1);
+ size = (end - start) >> (PAGE_SHIFT + 1);
+ }
if (size <= current_cpu_data.tlbsize/2) {
int oldpid = read_c0_entryhi();
int newpid = cpu_asid(cpu, mm);
- start &= (PAGE_MASK << 1);
- end += ((PAGE_SIZE << 1) - 1);
- end &= (PAGE_MASK << 1);
while (start < end) {
int idx;
write_c0_entryhi(start | newpid);
- start += (PAGE_SIZE << 1);
+ if (huge)
+ start += HPAGE_SIZE;
+ else
+ start += (PAGE_SIZE << 1);
mtc0_tlbw_hazard();
tlb_probe();
tlb_probe_hazard();
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