[PATCH 2/3 v2] MIPS: BCM63xx: remove BCM6345 hacks to read base boot address

[Florian Fainelli <florian@openwrt.org>]

Though BCM6345 does not technically have the same MPI register layout
than the other SoCs, reading the chip-select registers is done the same
way, and particularly for chip-select 0, which is the boot flash.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
Changes since v1:
- rebase against mips-for-linux-next
- folded patch 3 and 4 together

diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c 
b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 40b223b..ac948c2 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -709,15 +709,9 @@ void __init board_prom_init(void)
        char cfe_version[32];
        u32 val;
 
-       /* read base address of boot chip select (0)
-        * 6345 does not have MPI but boots from standard
-        * MIPS Flash address */
-       if (BCMCPU_IS_6345())
-               val = 0x1fc00000;
-       else {
-               val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-               val &= MPI_CSBASE_BASE_MASK;
-       }
+       /* read base address of boot chip select (0) */
+       val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+       val &= MPI_CSBASE_BASE_MASK;
        boot_addr = (u8 *)KSEG1ADDR(val);
 
        /* dump cfe version */
@@ -893,12 +887,9 @@ int __init board_register_devices(void)
                bcm63xx_dsp_register(&board.dsp);
 
        /* read base address of boot chip select (0) */
-       if (BCMCPU_IS_6345())
-               val = 0x1fc00000;
-       else {
-               val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-               val &= MPI_CSBASE_BASE_MASK;
-       }
+       val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+       val &= MPI_CSBASE_BASE_MASK;
+
        mtd_resources[0].start = val;
        mtd_resources[0].end = 0x1FFFFFFF;
 
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h 
b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 23403a3..5b8d15b 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -215,7 +215,7 @@ enum bcm63xx_regs_set {
 #define BCM_6345_ENETDMAS_BASE         (0xfffe2a00)
 #define BCM_6345_ENETSW_BASE           (0xdeadbeef)
 #define BCM_6345_PCMCIA_BASE           (0xfffe2028)
-#define BCM_6345_MPI_BASE              (0xdeadbeef)
+#define BCM_6345_MPI_BASE              (0xfffe2000)
 #define BCM_6345_OHCI0_BASE            (0xfffe2100)
 #define BCM_6345_OHCI_PRIV_BASE                (0xfffe2200)
 #define BCM_6345_USBH_PRIV_BASE                (0xdeadbeef)
-- 
1.7.5.4