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Re: [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definition

To: ddaney.cavm@gmail.com
Subject: Re: [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definitions for new chips.
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 16 Nov 2011 00:59:54 +0000
Cc: linux-mips@linux-mips.org, David Daney <david.daney@cavium.com>
In-reply-to: <1321400775-32353-2-git-send-email-ddaney.cavm@gmail.com>
References: <1321400775-32353-1-git-send-email-ddaney.cavm@gmail.com> <1321400775-32353-2-git-send-email-ddaney.cavm@gmail.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.21 (2010-09-15)
Queued for 3.3.  Thanks,

  Ralf

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