[PATCH 0/5] MIPS: Octeon: PCI{,e} updates for Octeon II SOCs

[ddaney.cavm@gmail.com]

From: David Daney <david.daney@cavium.com>

Nothing earth shattering.  The bulk of the change is the register
definitions for the new PCIe hardware.

David Daney (5):
  MIPS: Octeon: Update SOC PCI related register definitions for new
    chips.
  MIPS: Octeon: Update feature test functions for new chips and
    features.
  MIPS: Octeon: Update DMA mapping operations for OCTEON II processors.
  MIPS: Octeon: Update PCI Latency timer, PCIe payload, and PCIe max
    read to allow larger transactions
  MIPS: Octeon: Add support for OCTEON II PCIe

 arch/mips/cavium-octeon/dma-octeon.c             |   23 +-
 arch/mips/include/asm/octeon/cvmx-dpi-defs.h     |  643 +++++++
 arch/mips/include/asm/octeon/cvmx-npei-defs.h    |    4 +-
 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h |  609 ++++++-
 arch/mips/include/asm/octeon/cvmx-pemx-defs.h    |  509 +++++
 arch/mips/include/asm/octeon/cvmx-pexp-defs.h    |   19 +-
 arch/mips/include/asm/octeon/cvmx-sli-defs.h     | 2172 ++++++++++++++++++++++
 arch/mips/include/asm/octeon/cvmx-sriox-defs.h   | 1036 +++++++++++
 arch/mips/include/asm/octeon/cvmx.h              |   42 +-
 arch/mips/include/asm/octeon/octeon-feature.h    |  114 ++-
 arch/mips/include/asm/octeon/pci-octeon.h        |    3 +-
 arch/mips/pci/pci-octeon.c                       |   26 +-
 arch/mips/pci/pcie-octeon.c                      | 1349 ++++++++++----
 13 files changed, 6097 insertions(+), 452 deletions(-)
 create mode 100644 arch/mips/include/asm/octeon/cvmx-dpi-defs.h
 create mode 100644 arch/mips/include/asm/octeon/cvmx-pemx-defs.h
 create mode 100644 arch/mips/include/asm/octeon/cvmx-sli-defs.h
 create mode 100644 arch/mips/include/asm/octeon/cvmx-sriox-defs.h

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