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Re: [PATCH v2 01/11] MIPS: BCM63XX: set default pci cache line size.

To: Maxime Bizon <mbizon@freebox.fr>
Subject: Re: [PATCH v2 01/11] MIPS: BCM63XX: set default pci cache line size.
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 15 Nov 2011 19:54:38 +0000
Cc: linux-mips@linux-mips.org
In-reply-to: <1320430175-13725-2-git-send-email-mbizon@freebox.fr>
References: <1320430175-13725-1-git-send-email-mbizon@freebox.fr> <1320430175-13725-2-git-send-email-mbizon@freebox.fr>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.21 (2010-09-15)
On Fri, Nov 04, 2011 at 07:09:25PM +0100, Maxime Bizon wrote:

> +     pci_cache_line_size = 4;
> +

Presumably because the CPU cache line size is 16 bytes?  On MIPS we don't
set pci_dfl_cache_line_size; a patch (only compile tested) to pick a sane
default is below.

Does this work for you?

  Ralf

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

 arch/mips/pci/pci.c |   29 ++++++++++++++++++++++++++++-
 1 files changed, 28 insertions(+), 1 deletions(-)

diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 41af7fa..8ac0d48 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -4,8 +4,11 @@
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
- * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2011 Wind River Systems,
+ *   written by Ralf Baechle (ralf@linux-mips.org)
  */
+#include <linux/bug.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/bootmem.h>
@@ -14,6 +17,8 @@
 #include <linux/types.h>
 #include <linux/pci.h>
 
+#include <asm/cpu-info.h>
+
 /*
  * Indicate whether we respect the PCI setup left by the firmware.
  *
@@ -150,10 +155,32 @@ out:
               "Skipping PCI bus scan due to resource conflict\n");
 }
 
+static void __init pcibios_set_cache_line_size(void)
+{
+       struct cpuinfo_mips *c = &current_cpu_data;
+       unsigned int lsize;
+
+       /*
+        * Set PCI cacheline size to that of the highest level in the
+        * cache hierarchy.
+        */
+       lsize = c->dcache.linesz;
+       lsize = c->scache.linesz ? : lsize;
+       lsize = c->tcache.linesz ? : lsize;
+
+       BUG_ON(!lsize);
+
+       pci_dfl_cache_line_size = lsize >> 2;
+
+       pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
+}
+
 static int __init pcibios_init(void)
 {
        struct pci_controller *hose;
 
+       pcibios_set_cache_line_size();
+
        /* Scan all of the recorded PCI controllers.  */
        for (hose = hose_head; hose; hose = hose->next)
                pcibios_scanbus(hose);

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