| To: | Maxime Bizon <mbizon@freebox.fr> |
|---|---|
| Subject: | Re: [PATCH v2 00/11] MIPS: BCM63XX: add support for Broadcom 6368 CPU. |
| From: | Jonas Gorski <jonas.gorski@gmail.com> |
| Date: | Wed, 9 Nov 2011 13:43:00 +0100 |
| Cc: | ralf@linux-mips.org, linux-mips@linux-mips.org |
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| In-reply-to: | <1320430175-13725-1-git-send-email-mbizon@freebox.fr> |
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| Sender: | linux-mips-bounce@linux-mips.org |
Hi Maxime,
On 4 November 2011 19:09, Maxime Bizon <mbizon@freebox.fr> wrote:
>
> New in v2:
>
> Addressed all Jonas comments but the SPI register set. Since Florian
> and you have upcoming SPI drivers to submit, I'll let you decide which
> block deserves its own register set.
>
> External IRQ support has been changed slightly to handle more than 4
> irq, it now uses a fixed number range above 100. It has been tested on
> 6348/58/68.
Apart from patch 10/11 (and the nitpick regarding the {read,write}ll
-> q) these look all fine to me. Thanks for your work!
Regards,
Jonas
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