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[PATCH 15/18] MIPS: Alchemy: remove unused board headers

To: Linux-MIPS <linux-mips@linux-mips.org>, Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH 15/18] MIPS: Alchemy: remove unused board headers
From: Manuel Lauss <manuel.lauss@googlemail.com>
Date: Tue, 1 Nov 2011 20:03:41 +0100
Cc: Manuel Lauss <manuel.lauss@googlemail.com>
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In-reply-to: <1320174224-27305-1-git-send-email-manuel.lauss@googlemail.com>
References: <1320174224-27305-1-git-send-email-manuel.lauss@googlemail.com>
Sender: linux-mips-bounce@linux-mips.org
The information in those headers is no longer necessary.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
 arch/mips/alchemy/Platform                 |    3 -
 arch/mips/include/asm/mach-db1x00/db1x00.h |   63 ------------------------
 arch/mips/include/asm/mach-pb1x00/pb1550.h |   73 ----------------------------
 3 files changed, 0 insertions(+), 139 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-db1x00/db1x00.h
 delete mode 100644 arch/mips/include/asm/mach-pb1x00/pb1550.h

diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index 33f80e8..7956274 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -8,21 +8,18 @@ platform-$(CONFIG_MIPS_ALCHEMY)       += alchemy/common/
 # AMD Alchemy Pb1100 eval board
 #
 platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1100)   += 
-I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1100)     += 0xffffffff80100000
 
 #
 # AMD Alchemy Pb1500 eval board
 #
 platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1500)   += 
-I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1500)     += 0xffffffff80100000
 
 #
 # AMD Alchemy Pb1550 eval board
 #
 platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1550)   += 
-I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1550)     += 0xffffffff80100000
 
 #
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h 
b/arch/mips/include/asm/mach-db1x00/db1x00.h
deleted file mode 100644
index 51f1ebf..0000000
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * AMD Alchemy DBAu1x00 Reference Boards
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_DB1X00_H
-#define __ASM_DB1X00_H
-
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-/*
- * NAND defines
- *
- * Timing values as described in databook, * ns value stripped of the
- * lower 2 bits.
- * These defines are here rather than an Au1550 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H               (18 >> 2)
-#define NAND_T_PUL             (30 >> 2)
-#define NAND_T_SU              (30 >> 2)
-#define NAND_T_WH              (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT         0
-#define NAND_T_PUL_SHIFT       4
-#define NAND_T_SU_SHIFT                8
-#define NAND_T_WH_SHIFT                12
-
-#define NAND_TIMING    (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                        ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                        ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                        ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-#define NAND_CS        1
-
-/* Should be done by YAMON */
-#define NAND_STCFG     0x00400005 /* 8-bit NAND */
-#define NAND_STTIME    0x00007774 /* valid for 396 MHz SD=2 only */
-#define NAND_STADDR    0x12000FFF /* physical address 0x20000000 */
-
-#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h 
b/arch/mips/include/asm/mach-pb1x00/pb1550.h
deleted file mode 100644
index 443b88a..0000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * AMD Alchemy Semi PB1550 Reference Board
- * Board Registers defines.
- *
- * Copyright 2004 Embedded Edge LLC.
- * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1550_H
-#define __ASM_PB1550_H
-
-#include <linux/types.h>
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#define DBDMA_AC97_TX_CHAN     AU1550_DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN     AU1550_DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN      AU1550_DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN      AU1550_DSCR_CMD0_PSC3_RX
-
-#define SPI_PSC_BASE           AU1550_PSC0_PHYS_ADDR
-#define AC97_PSC_BASE          AU1550_PSC1_PHYS_ADDR
-#define SMBUS_PSC_BASE         AU1550_PSC2_PHYS_ADDR
-#define I2S_PSC_BASE           AU1550_PSC3_PHYS_ADDR
-
-/*
- * Timing values as described in databook, * ns value stripped of
- * lower 2 bits.
- * These defines are here rather than an SOC1550 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H               (18 >> 2)
-#define NAND_T_PUL             (30 >> 2)
-#define NAND_T_SU              (30 >> 2)
-#define NAND_T_WH              (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT         0
-#define NAND_T_PUL_SHIFT       4
-#define NAND_T_SU_SHIFT                8
-#define NAND_T_WH_SHIFT                12
-
-#define NAND_TIMING    (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                        ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                        ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                        ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-
-#define NAND_CS 1
-
-/* Should be done by YAMON */
-#define NAND_STCFG     0x00400005 /* 8-bit NAND */
-#define NAND_STTIME    0x00007774 /* valid for 396 MHz SD=2 only */
-#define NAND_STADDR    0x12000FFF /* physical address 0x20000000 */
-
-#endif /* __ASM_PB1550_H */
-- 
1.7.7.1


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