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Re: cause IP zero on interrupt

To: David Daney <david.daney@cavium.com>
Subject: Re: cause IP zero on interrupt
From: Guenter Roeck <guenter.roeck@ericsson.com>
Date: Fri, 21 Oct 2011 13:48:54 -0700
Cc: Noor <noor.mubeen@gmail.com>, "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>
In-reply-to: <4EA1D87A.1090708@cavium.com>
Organization: Ericsson
References: <CAMmEz3QV+kWvRK9KnUdmKFGqNA8XUspjc_cH7aYXfea5XYaRAg@mail.gmail.com> <4EA1D87A.1090708@cavium.com>
Reply-to: guenter.roeck@ericsson.com
Sender: linux-mips-bounce@linux-mips.org
On Fri, 2011-10-21 at 16:39 -0400, David Daney wrote:
> On 10/21/2011 01:18 PM, Noor wrote:
> > what does it mean if cause register IP bits are zero after
> > interrupt exception  has already been invoked ?
> >
> 
> It might mean that something was asserting a '1' on to those bits, but 
> quit doing so before you could read the cause register, or it could be 
> that you get random interrupt exceptions for no reason at all.
> 

In my case it was the following:

diff --git
a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index dedef7d..7500c55 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -63,6 +63,10 @@
        # CN30XX Disable instruction prefetching
        or  v0, v0, 0x2000
 skip:
+#ifdef CONFIG_ERICSSON_ASE
+       # Set CvmCtl[IPTI] to 7
+       ori     v0, v0, (7 << 4)
+#endif
        # First clear off CvmCtl[IPPCI] bit and move the performance
        # counters interrupt to IRQ 6
        li      v1, ~(7 << 7)

This should not be needed in the Linux code, but CvmCtl[IPTI] was set to
0 by ROMMON.

Guenter



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