| To: | Paul_Koning@Dell.com |
|---|---|
| Subject: | Re: $ta0 .. $ta3 registers in O32 on MIPS |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Wed, 28 Sep 2011 21:43:20 +0200 |
| Cc: | binutils@sourceware.org, linux-mips@linux-mips.org, dvdkhlng@gmx.de |
| In-reply-to: | <09787EF419216C41A903FD14EE5506DD030987ABAE@AUSX7MCPC103.AMER.DELL.COM> |
| References: | <20110928123305.GA1971@linux-mips.org> <09787EF419216C41A903FD14EE5506DD030987ABAE@AUSX7MCPC103.AMER.DELL.COM> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.21 (2010-09-15) |
On Wed, Sep 28, 2011 at 10:11:40AM -0500, Paul_Koning@Dell.com wrote: > >I was expecting an error message and I'm wondering, was this intentional? > > I would say so. I call this a feature. It makes it easier to write assembly > code that assembles without change in both O32 and N32/N64. Consider a > function that has 4 or fewer arguments, but needs a pile of scratch > registers. It can use ta0-ta3 as four scratch registers, which is correct in > all the ABIs. Turns out that later IRIX version also retroactively introduced the ta registers for O32 and I just never noticed. So I'm going to change the Linux kernel headers for consistence and compatibility with everybody else. Ralf |
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