|To:||Deng-Cheng Zhu <email@example.com>, firstname.lastname@example.org|
|Subject:||Re: [PATCH v5 4/5] MIPS: perf: Add support for 64-bit perf counters.|
|From:||David Daney <email@example.com>|
|Date:||Sat, 24 Sep 2011 13:57:40 -0700|
|Cc:||David Daney <firstname.lastname@example.org>, email@example.com, Peter Zijlstra <firstname.lastname@example.org>, Paul Mackerras <email@example.com>, Ingo Molnar <firstname.lastname@example.org>, Arnaldo Carvalho de Melo <email@example.com>|
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On 09/23/2011 07:54 PM, Deng-Cheng Zhu wrote:
It doesn't make the maximum overflow period any shorter. It just hides it from the perf core, which is perfectly capable of handling the shorter maximum overflow period.2011/9/23 David Daney<firstname.lastname@example.org>:The hard coded constants are moved to struct mips_pmu. All counter register access move to the read_counter and write_counter function pointers, which are set to either 32-bit or 64-bit access methods at initialization time. Many of the function pointers in struct mips_pmu were not needed as there was only a single implementation, these were removed. I couldn't figure out what made struct cpu_hw_events.msbs at all useful, so I removed it too.The idea behind msbs is to simulate 32-bit counters based on the fact of MIPS using the MSB to trigger the overflow interrupt. By doing this, the average length of the overflow ISR can be shorter in the case of event period is bigger than 0x80000000.
Also, it simplifies counter value related algorithms in the code
Have you looked at the code? It in no way simplifies things. The patch removes 80 lines of code while maintaining 32-bit counter support *and* adding 64-bit support.
- most of other architectures have 32-bit counters instead of 31-bit. In addition, taking over those bugfixes can be easier as a concequence.
Not the Linux way. If there are bugs in the perf core we fix them, we don't work around them in archecture specific code.
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