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Re: [PATCH v5 4/5] MIPS: perf: Add support for 64-bit perf counters.

To: David Daney <david.daney@cavium.com>
Subject: Re: [PATCH v5 4/5] MIPS: perf: Add support for 64-bit perf counters.
From: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Date: Sat, 24 Sep 2011 10:54:41 +0800
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, Peter Zijlstra <a.p.zijlstra@chello.nl>, Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@elte.hu>, Arnaldo Carvalho de Melo <acme@redhat.com>
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In-reply-to: <1316712378-7282-5-git-send-email-david.daney@cavium.com>
References: <1316712378-7282-1-git-send-email-david.daney@cavium.com> <1316712378-7282-5-git-send-email-david.daney@cavium.com>
Sender: linux-mips-bounce@linux-mips.org
2011/9/23 David Daney <david.daney@cavium.com>:
> The hard coded constants are moved to struct mips_pmu.  All counter
> register access move to the read_counter and write_counter function
> pointers, which are set to either 32-bit or 64-bit access methods at
> initialization time.
>
> Many of the function pointers in struct mips_pmu were not needed as
> there was only a single implementation, these were removed.
>
> I couldn't figure out what made struct cpu_hw_events.msbs[] at all
> useful, so I removed it too.

The idea behind msbs is to simulate 32-bit counters based on the fact
of MIPS using the MSB to trigger the overflow interrupt. By doing this, the
average length of the overflow ISR can be shorter in the case of event
period is bigger than 0x80000000. Also, it simplifies counter value related
algorithms in the code - most of other architectures have 32-bit counters
instead of 31-bit. In addition, taking over those bugfixes can be easier as
a concequence.


Deng-Cheng

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