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Re: [PATCH] MIPS: SMTC: Correct saving of CP0_STATUS

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH] MIPS: SMTC: Correct saving of CP0_STATUS
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Date: Sat, 17 Sep 2011 04:08:49 +0200
Cc: David Daney <david.daney@cavium.com>, linux-mips@linux-mips.org, "Kevin D. Kissell" <kevink@paralogos.com>
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On Sat, Sep 17, 2011 at 04:00:32AM +0200, Ralf Baechle wrote:
> On Sat, Sep 17, 2011 at 03:23:15AM +0200, Edgar E. Iglesias wrote:
> 
> > I agree, thanks!
> 
> You're welcome.
> 
> > BTW, in case anyone is intersted, it is now possible to boot malta
> > boards with SMP with the latest QEMU. The neat thing is that if you
> > debug the kernel with GDB, you'll see the different cores execution
> > contexts as differten threads and can singletep them individually.
> 
> Very interesting.  What type of SMP system does it emulate?

I'm not all familiar with the terminology, but it works with the kind
where you've got multiple VPEs with one TC per VPE, vSMP IIUC.

You need to pass these options to QEMU, -cpu 34Kf -smp 2, where 2 maybe
anything up to 16.

We've (AXIS) got models for the GIC aswell, but I need to check with MTI 
before publishing those.  IMO these models would help everybody cause
it's, to say the leaast, a huge pain to setup the GIC without having QEMU
or any emulator to check the interrupt routing.

Cheers

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