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Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu

To: David Daney <david.daney@cavium.com>
Subject: Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu
From: SAURABH MALPANI <saurabh140585@gmail.com>
Date: Wed, 7 Sep 2011 00:51:59 +0530
Cc: linux-mips@linux-mips.org
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On Wed, Sep 7, 2011 at 12:47 AM, David Daney <david.daney@cavium.com> wrote:
> On 09/06/2011 12:02 PM, SAURABH MALPANI wrote:
>>
>> Hi David,
>>
>> Thanks a bunch for clarifying this. Just to complete, I have some code
>> which calls CHECK_IRQ_PER_CPU(desc->status) after every time a
>> descriptor is created for an irq. And based on it we create either per
>> cpu data structures or single data structure for that particular irq.
>>
>> After your clarification, I can safely create exception for
>> OCTEON_IRQ_MBOX0 and OCTEON_IRQ_MBOX1 as you mention that missing the
>> flag is just cosmetic.
>>
>
> Well the performance counter and timer interrupts may suffer in a similar
> manner.
>
> David Daney
>


Since the timer interrupt is registered via the clock device
infrastructure, I found that hrtimer_interrupt irq descriptor was
indeed succeeding the CHECK_IRQ_PER_CPU test. So far in our testing we
only hit an exception for mailbox interrupt.

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